Virtual network pre-arbitration for deadlock avoidance and enhanced performance

1. A device comprising:

a data path;

a first interface configured to receive a first memory access request from a first peripheral device;

a second interface configured to receive a second memory access request from a second peripheral device; and

an arbiter circuit configured to:

in a first clock cycle:

determine a first destination device connected to the data path and associated with the first memory access request and a first credit threshold corresponding to the first memory access request;

determine a second destination device connected to the data path and associated with the second memory access request and a second credit threshold corresponding to the second memory access request; and

select a pre-arbitration winner between the first memory access request and the second memory access request based on a comparison of the first credit threshold to a first number of credits allocated to the first destination device and a comparison of the second credit threshold to a second number of credits allocated to the second destination device; and

in a second clock cycle:

select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request; and

drive the final arbitration winner to the data path.

2. The device of claim 1 , wherein the arbiter circuit is configured to select the first memory access request as the pre-arbitration winner in response to the first number of credits satisfying the first credit threshold and the second number of credits failing to satisfy the second credit threshold.

3. The device of claim 1 , wherein the arbiter circuit is configured to select the pre-arbitration winner based further on a fair-share algorithm in response to the first number of credits satisfying the first credit threshold and the second number of credits satisfying the second credit threshold.

4. The device of claim 1 , wherein the arbiter circuit is configured to select the pre-arbitration winner based further on a round robin algorithm in response to the first number of credits satisfying the first credit threshold and the second number of credits satisfying the second credit threshold.

5. The device of claim 1 , wherein the arbiter circuit is configured to select the pre-arbitration winner based further on a first priority level of the first memory access request and a second priority level of the second memory access request in response to the first number of credits satisfying the first credit threshold and the second number of credits satisfying the second credit threshold.

6. The device of claim 1 , further comprising a configuration register configured to store a starvation threshold associated with the first interface, wherein the arbiter circuit is configured to select the pre-arbitration winner based further on a comparison of the starvation threshold to a count of cycles the first memory access request has lost arbitration to the starvation threshold in response to the first number of credits satisfying the first credit threshold and the second number of credits satisfying the second credit threshold.

7. The device of claim 6 , further comprising a configuration arbiter circuit connected to the data path and configured to arbitrate access to the configuration register.

8. The device of claim 1 , further comprising:

a memory bank;

a read-modify-write queue connected to the memory bank and to the data path, the read-modify-write queue configured to arbitrate access to the memory bank.

9. The device of claim 8 , further comprising:

a second memory bank; and

a second read-modify-write queue connected to the second memory bank and to the data path, the second read-modify-write queue configured to arbitrate access to the second memory bank.

10. The device of claim 9 , further comprising:

an external memory interface; and

an external memory arbiter connected to the external memory interface, to the read-modify-write queue, and to the second read-modify-write queue, wherein the read-modify-write queue and the second read-modify-write queue are further configured to arbitrate access to the external memory arbiter, and wherein the external memory arbiter is configured to arbitrate access to the external memory interface.

11. A system comprising:

a first processor package;

a second processor package; and

a multi-core shared memory controller (MSMC) including:

a data path;

a first interface connected to the first processor package and configured to receive a first memory access request from the first processor package;

a second interface connected to the second processor package and configured to receive a second memory access request from the second processor package; and

an arbiter circuit configured to:

in a first clock cycle:

determine a first destination device connected to the data path and associated with the first memory access request and a first credit threshold corresponding to the first memory access request;

determine a second destination device connected to the data path and associated with the second memory access request and a second credit threshold corresponding to the second memory access request; and

select a pre-arbitration winner between the first memory access request and the second memory access request based on a comparison of the first credit threshold to a first number of credits allocated to the first destination device and a comparison of the second credit threshold to a second number of credits allocated to the second destination device; and

in a second clock cycle:

select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request; and

drive the final arbitration winner to the data path.

12. The system of claim 11 , wherein the arbiter circuit is configured to select the first memory access request as the pre-arbitration winner in response to the first number of credits satisfying the first credit threshold and the second number of credits failing to satisfy the second credit threshold.

13. The system of claim 11 , wherein the arbiter circuit is configured to select the pre-arbitration winner based further on a fair-share algorithm in response to the first number of credits satisfying the first credit threshold and the second number of credits satisfying the second credit threshold.

14. The system of claim 11 , wherein the arbiter circuit is configured to select the pre-arbitration winner based further on a first priority level of the first memory access request and a second priority level of the second memory access request in response to the first number of credits satisfying the first credit threshold and the second number of credits satisfying the second credit threshold.

15. The system of claim 11 , wherein the MSMC further includes a configuration register configured to store a starvation threshold associated with the first interface, and wherein the arbiter circuit is configured to select the pre-arbitration winner based further on a comparison of the starvation threshold to a count of cycles the first memory access request has lost arbitration to the starvation threshold in response to the first number of credits satisfying the first credit threshold and the second number of credits satisfying the second credit threshold.

16. The system of claim 15 , wherein the MSMC further includes a configuration arbiter circuit connected to the data path and configured to arbitrate access to the configuration register.

17. The system of claim 11 , wherein the MSMC further includes:

a memory bank;

a read-modify-write queue connected to the memory bank and to the data path, the read-modify-write queue configured to arbitrate access to the memory bank.

18. The system of claim 17 , wherein the MSMC further includes:

a second memory bank; and

a second read-modify-write queue connected to the second memory bank and to the data path, the second read-modify-write queue configured to arbitrate access to the second memory bank.

19. The system of claim 18 , further comprising:

an external memory device, wherein the MSMC further includes:

an external memory interface connected to the external memory device; and

an external memory arbiter connected to the external memory interface, to the read-modify-write queue, and to the second read-modify-write queue, wherein the read-modify-write queue and the second read-modify-write queue are further configured to arbitrate access to the external memory arbiter, and wherein the external memory arbiter is configured to arbitrate access to the external memory interface.

20. A method comprising:

receiving, at an arbitration circuit, a first memory access request from a first processor package connected to a first interface;

receiving, at the arbitration circuit, a second memory access request from a second processor package connected to a second interface;

in a first clock cycle:

determining, at the arbitration circuit, a first destination device associated with the first memory access request and a first credit threshold corresponding to the first memory access request;

determining, at the arbitration circuit, a second destination device associated with the second memory access request and a second credit threshold corresponding to the second memory access request; and

selecting a pre-arbitration winner between the first memory access request and the second memory access request based on a comparison of the first credit threshold to a first number of credits allocated to the first destination device and a comparison of the second credit threshold to a second number of credits allocated to the second destination device; and

in a second clock cycle:

selecting a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request; and

driving the final arbitration winner to the data path.