Universal automatic frequency control for multi-channel receivers

1. A data receiver, comprising:

a tuner for receiving a first signal and a second signal;

a first demodulator coupled to the tuner, the first demodulator being configured to demodulate the first signal;

a second demodulator coupled to the tuner, the second demodulator being configured to demodulate the second signal; and

at least one processor coupled to the first and second demodulators, the at least one processor being configured to determine a first frequency offset for the first demodulator,

wherein, when the second demodulator is unable to lock to the second signal, the at least one processor applies the first frequency offset to the second demodulator.

2. The data receiver of claim 1 , wherein the second demodulator demodulates the second signal based on the first frequency offset.

3. The data receiver of claim 2 , wherein the at least one processor triggers an update signal for updating unlocked demodulators coupled to the tuner if the first demodulator has drifted.

4. The data receiver of claim 1 , wherein when the second demodulator is locked to the second signal, the at least one processor determines that a frequency drift of the second demodulator is greater than a predetermined frequency drift threshold.

5. The data receiver of claim 4 , wherein the at least one processor calculates a sample frequency offset based on the frequency drift of the second demodulator.

6. The data receiver of claim 1 , wherein the at least one processor updates phase and an interpolation ratio for the second demodulator based on the sample frequency offset and the first frequency offset.

7. The data receiver of claim 1 , wherein the at least one processor resets the front end bulk search and timing of second order loops.

8. A method, comprising:

receiving, by a tuner, a plurality of modulated signals;

designating, by at least one processor, one of the plurality of modulated signals as a reference signal;

detecting, by the at least one processor, that a first demodulator is locked onto a first signal of the plurality of modulated signals;

determining, by the at least one processor, that a frequency drift of the first demodulator satisfies a predetermined threshold drift; and

responsive to the frequency drift satisfying the predetermined threshold drift:

calculating, by the at least one processor, a frequency offset associated with the reference signal; and

adjusting, by the first demodulator and based on the frequency offset, the first modulated signal to generate a first demodulated signal.

9. The method of claim 8 , further comprising:

calculating a sample frequency offset based on the frequency offset.

10. The method of claim 8 , wherein the designating the one of the plurality of modulated signals as a reference signal is based on the signal satisfying an expected signal integrity.

11. The method of claim 10 , wherein the satisfying the expected signal integrity is based on determining at least one of: an expected signal-to-noise ratio, constellation point variations, and calculating a difference between a second order value and a nominal default value.

12. The method of claim 8 , further comprising:

determining, by the at least one processor, that the reference signal is associated with a frequency drift;

detecting, by the at least one processor, a second demodulator that is unlocked; and

adjusting, by the at least one processor, a demodulator offset value and a sample frequency offset value associated with the second demodulator based on the frequency drift of the reference signal.

13. The method of claim 12 , further comprising:

adjusting, by the at least one processor, frequency offset values for a remaining number of unlocked demodulators based on the frequency drift.

14. The method of claim 13 , further comprising:

updating interpolation ratios and center frequency phase increments respectively corresponding to the unlocked demodulators.

15. A method, comprising:

receiving, by a tuner and over a satellite broadcast, a plurality of signals, wherein the plurality of signals are respectively demodulated by a plurality of demodulators;

designating, by at least one processor, one of the plurality of demodulators as a reference demodulator based on a predefined order;

determining, by at least one processor, that a first demodulator of the plurality of demodulators is unable to lock to a corresponding first signal of the plurality of signals; and

applying, by the at least one processor, a reference frequency offset associated with the reference demodulator to the first demodulator, wherein the reference frequency offset is based on a frequency offset between a reference signal being received by the reference demodulator and an oscillator.

16. The method of claim 15 , wherein the reference signal is one of the plurality of signals, and wherein the designating the one of the plurality of demodulators as the reference demodulator is further based on determining that the demodulator is locked onto the reference signal.

17. The method of claim 16 , further comprising:

identifying, by at least one processor, a second demodulator of the plurality of demodulators that is locked onto a second signal of the plurality of signals; and

calculating, by at least one processor, a sample frequency offset for the second demodulator.

18. The method of claim 17 , further comprising:

storing the sample frequency offset in a memory.

19. The method of claim 17 , further comprising:

determining that the reference frequency offset has been applied to a remaining number of unlocked demodulators; and

updating center frequency phase increments and interpolation ratios respectively associated with the unlocked demodulators.

20. The method of claim 19 , further comprising:

resetting register values associated with the unlocked demodulators.