Data communication systems with forward error correction
Embodiments of the present invention include an apparatus that receives date from multiple lanes, which are then aligned and synchronized for transcoding and encoding.
1. A communication apparatus operable in 25G, 40G, 50G, and 100G modes, the apparatus comprising:
a plurality of communication lanes, each of communication lanes being configured to receive data streams;
a plurality of virtual lane lock modules corresponding to the plurality of communication lanes, the virtual lane lock modules being configured to provide protocol locking at a first clock rate;
a plurality of de-skewing buffers for aligning data streams of the plurality of communication lanes;
a transcoder module being configured to generate alternating data streams from the de-skewed data stream, the transcoder being configured to operate at a second clock rate, the transcoder being operative in two or more modes;
an FEC module being configured to encode the alternating data streams to generate a first encoded data stream and a second encoded data stream at a first bit size and a first cycle number; and
a first gearbox configured to process the first encoded data stream at a second bit size and a second cycle number.
2. The apparatus of claim 1 further comprising a second gearbox configured to process the second encoded data stream at the second bit size and the second cycle number.
3. The apparatus of claim 1 further comprising a pattern generator coupled to the second gearbox.
4. The apparatus of claim 1 wherein the transcoder is operative in 40 Gbps PAM-4 mode and 100 Gbps PAM-8 mode.
5. The apparatus of claim 4 wherein the transcoder processes input in every clock cycle when operating in the 100 Gbps PAM-8 mode.
6. The apparatus of claim 5 wherein the transcoder processes input in every four clock cycles when operating in the 40 Gbps PAM-4 mode.
7. The apparatus of claim 1 further comprising an alignment module for aligning the received data streams.
8. The apparatus of claim 7 wherein the plurality of virtual lane lock modules is configured to provide BIP check.
9. The apparatus of claim 7 wherein the alignment module is configured to insert alignment markers at predetermined locations.
10. The apparatus of claim 1 further comprising a first MUX device coupled to a first output of a first gearbox.
11. The apparatus of claim 10 wherein the first MUX device is configured to select outputs based on at least a PRBS mode.
12. The apparatus of claim 1 wherein the transcoder concatenates a predetermined number of words from the aligned data stream.
13. The apparatus of claim 1 wherein the plurality of virtual lane locks provides block synchronization.
14. The apparatus of claim 1 wherein the alignment module comprising an alignment mapper.
15. The apparatus of claim 1 wherein the plurality of virtual lane locks comprises a finite state machine for providing block lock.
16. The apparatus of claim 15 wherein the finite state machine is configured to check a validity status associated with synchronization headers.
17. The apparatus of claim 15 wherein the finite state machine is further configured to update a count for the synchronization headers.
18. The apparatus of claim 1 further comprising a bit-error-rate monitor coupled to the de-skewing buffer.
19. A communication apparatus comprising:
a plurality of virtual lane lock modules configured to provide protocol locking at a first clock rate based on received data streams;
a plurality of de-skewing buffers for aligning data streams of the plurality of communication lanes;
a transcoder module being configured to generate alternating data streams from the de-skewed data stream, the transcoder being configured to operate at a second clock rate, the transcoder being operative in two or more modes;
an FEC module being configured to encode the alternating data streams to generate a first encoded data stream and a second encoded data stream at a first bit size and a first cycle number;
a first gearbox configured to process the first encoded data stream at a second bit size and a second cycle number;
a second gearbox configured to process the second encoded data stream at the second bit size and the second cycle number; and
a pattern generator coupled to the first gearbox.
20. A communication apparatus comprising:
a plurality of virtual lane lock modules configured to provide protocol locking at a first clock rate based on received data streams;
an alignment module being configured to generate an aligned data stream based on locked streams from the plurality of virtual lane lock modules, the alignment module being configured to operate at a second clock rate, the aligned data stream comprising a first plurality of words, the first plurality of words being characterized by a first word length;
a transcoder module being configured to generate alternating data streams based using the aligned data stream, the transcoder being configured to operate at a third clock rate, the alternating data streams comprising a second plurality of words, the second plurality of words being characterized by a second word length, the transcoder being operative in two or more modes; and
an FEC module being configured to encode the alternating data streams to generate an encoded data stream at a first bit size;
a gearbox configured to process the encoded data stream at a second bit size; and
a pattern generator coupled to the gearbox.