METHODS AND SYSTEMS FOR DIGITAL BEAMFORMING
Systems and methods are provided for utilizing antenna arrays with digital beamforming. An array-based system may have a plurality of antenna elements arranged in a two-dimensional array, and a plurality of transceiver chips configured for handling transmission and reception of radio frequency (RF) signals via the plurality of antenna elements. A number of transceiver chips in the plurality of transceiver chips may be less than a number of antenna elements in the plurality of antenna elements. The plurality of transceiver chips is configured to control operation of the plurality of antenna elements such that digital or hybrid beamforming is enabled during the transmission and reception of RF signals via the plurality of antenna elements.
1 . A system, comprising:
a plurality of antenna elements arranged in two-dimensional array;
a plurality of transceiver chips configured for handling transmission and reception of radio frequency (RF) signals via the plurality of antenna elements;
wherein:
a number of transceiver chips in the plurality of transceiver chips is less than a number of antenna elements in the plurality of antenna elements; and
the plurality of transceiver chips is configured to control operation of the plurality of antenna elements such that digital or hybrid beamforming is enabled during the transmission and reception of RF signals via the plurality of antenna elements.
2 . The system of claim 1 , wherein at least one transceiver chip from the plurality of transceiver chips is configured to control and/or handle two or more antenna elements from the plurality of antenna elements.
3 . The system of claim 1 , wherein each transceiver chip from the plurality of transceiver chips is configured to control and/or handle two or more antenna elements from the plurality of antenna elements.
4 . The system of claim 3 , wherein each transceiver chip from the plurality of transceiver chips is configured to control and/or handle four antenna elements from the plurality of antenna elements.
5 . The system of claim 1 , wherein the plurality of transceiver chips are arranged on a back-side of the two-dimensional array.
6 . The system of claim 1 , wherein the plurality of transceiver chips are embedded within the two-dimensional array.
7 . The system of claim 1 , comprising at least one digital precoding chip.
8 . The system of claim 1 , comprising one or more connectors configuring for enabling communications among the plurality of transceiver chips, and communications within the system, to and/or from each of the plurality of transceiver chips.
9 . The system of claim 8 , wherein the one or more connectors comprise on-chip based Serializer/Deserializer (SerDes) connectors.
10 . The system of claim 8 , wherein each transceiver chip in the plurality of transceiver chips comprises an interface circuit configured for handling communications to and/or from the transceiver chip, via the one or more connectors.
11 . The system of claim 1 , wherein each transceiver chip in the plurality of transceiver chips comprises one or more circuits for handling signals transmitted and received via at least one antenna element in the plurality of antenna elements.
12 . The system of claim 11 , wherein each transceiver chip comprises one or more digital phase shift and combiner circuits.
13 . The system of claim 11 , wherein each transceiver chip comprises a timing control circuit configured for providing shared timing signals for driving circuits in the transceiver chips used in handling the transmitted and received signals.
14 . The system of claim 11 , wherein a transceiver chip in the plurality of transceiver chips that control and/or handle two or more antenna elements, the one or more circuits comprise corresponding two or more circuits each configured for handling different one of the two or more antenna elements.
15 . A transceiver chip configured for handling transmission and reception of radio frequency (RF) signals via two or more antenna elements from a plurality of antenna elements in an array-based system; the transceiver chip comprising:
a plurality of circuits that comprise at least at least two sets of circuits corresponding to the two or more antenna elements;
wherein:
each set of circuits is configured for handling signals transmitted and received via a corresponding antenna element; and
the transceiver chip is configured to control operation of the two or more antenna elements such that digital or hybrid beamforming is enabled during the transmission and reception of RF signals via the plurality of antenna elements.
16 . The transceiver chip of claim 14 , wherein each set of circuits comprises a digital phase shift and combiner circuit.
17 . The transceiver chip of claim 14 , wherein each set of circuits comprises two separate sub-sets arranged for separately handling transmitted signals and received signals.
18 . The transceiver chip of claim 14 , wherein the plurality of circuits comprises a timing control circuit configured for providing shared timing signals for driving the sets of circuits.
19 . The transceiver chip of claim 14 , wherein the plurality of circuits comprises an interface circuit configured for handling communications to and/or from the transceiver chip, within the array-based system.
20 . The system of claim 19 , wherein the interface circuit is configured for handling Serializer/Deserializer (SerDes) based communications.