IP Library Granted Patent US 11,212,179
Granted Patent B2
US 11,212,179 · App. 16/660,721 · Granted Dec 28, 2021

Automatic configuration of a network switch in a multi-chassis link aggregation group

Inventor: Sahul Hameed Abdul Kader Jailani (San Jose, CA)
Assignee: SUPER MICRO COMPUTER, INC.
H04L41/0886H04L12/40H04L12/413H04L41/0806H04L41/12H04L45/245
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Quick Facts
Patent No.
US 11,212,179
App. No.
16/660,721
Granted
Dec 28, 2021
Kind
B2
Abstract

Various embodiments set forth a method for automatically configuring a multi-chassis link aggregation group (MLAG), including receiving first system information associated with the MLAG, receiving a first discovery packet via a first uplink port associated with a first switch that is included in the MLAG, where the first discovery packet includes second system information associated with the MLAG, determining whether the first system information matches the second system information, where if the first system information matches the second system information, then concluding that the first uplink port is included in an inter peer link connecting the first switch to a second switch that also is included in the MLAG, and if the first system information does not match the second system information, then concluding that the first uplink port is not included in the inter peer link. Advantageously, the method avoids requiring a user to enter hundreds of commands manually.

Claims (43)

1. A computer-implemented method, comprising:

receiving a first discovery packet via a first uplink port associated with a first switch that is included in a multi-chassis link aggregation group (MLAG);

determining that first system information associated with the MLAG matches second system information associated with the MLAG and included in the first discovery packet; and

in response to the determining, concluding that the first uplink port is included in an inter-peer link connecting the first switch to a second switch that is included in the MLAG.

2. The computer-implemented method of claim 1 , further comprising:

receiving a second discovery packet via a second uplink port associated with a third switch;

determining that the first system information does not match third system information included in the second discovery packet; and

in response to the determining, concluding that the second uplink port is not coupled via an inter-peer link to another switch that is included in the MLAG.

3. The computer-implemented method of claim 1 , wherein the first system information includes a first system identifier associated with the MLAG, and the second system information includes a second system identifier associated with the MLAG.

4. The computer-implemented method of claim 3 , wherein the first system identifier associated with the MLAG is received via a command line interface.

5. The computer-implemented method of claim 3 , wherein the first system information further indicates a first model number associated with the first switch, and the second system information further indicates a second model number associated with the second switch.

6. The computer-implemented method of claim 5 , wherein the first system information matches the second system information if the first system identifier matches the second system identifier and if the first model number matches the second model number.

7. The computer-implemented method of claim 5 , wherein the first system information does not match the second system information if the first system identifier does not match the second system identifier or if the first model number does not match the second model number.

8. The computer-implemented method of claim 1 , wherein the first system information matches the second system information, and further comprising:

determining that the first uplink port is not already included in the inter-peer link;

adding the first uplink port to a list of uplink ports that are included in the inter-peer link; and

configuring the first uplink port to be part of the inter-peer link connecting the first switch to the second switch.

9. The computer-implemented method of claim 1 , wherein the first system information does not match the second system information, and further comprising:

determining that the first uplink port is already included in the inter-peer link; and

removing the first uplink port from a list of uplink ports that are included in the inter-peer link.

10. The computer-implemented method of claim 1 , further comprising transmitting discovery packets via the first uplink port at periodic intervals having a first time period.

11. The computer-implemented method of claim 10 , further comprising:

determining that a second time period has elapsed since receiving a most recent discovery packet via the first uplink port, wherein the second time period is greater than the first time period; and

concluding that the first uplink port is not included in the inter-peer link.

12. The computer-implemented method of claim 1 , wherein at least one of the first system information and the second system information includes a system identifier from which a common MAC address for the first switch and the second switch is derived.

13. The computer-implemented method of claim 1 , wherein the first switch executes an auto-M LAG module that determines the first system information and the second system information.

14. The computer-implemented method of claim 13 , wherein the auto-MLAG module further configures the inter-peer link connecting the first switch to the second switch.

15. The computer-implemented method of claim 13 , wherein the auto-MLAG module further configures connections between a first set of downlink ports included in the first switch and one or more downlink devices.

16. The computer-implemented method of claim 15 , wherein the auto-M LAG module further configures connections between a second set of downlink ports included in the second switch and the one or more downlink devices.

17. The computer-implemented method of claim 13 , wherein a computing device external to the first switch and the second switch causes the first switch to execute the auto-MLAG module.

18. The computer-implemented method of claim 1 , wherein a computing device external to the first switch and the second switch:

causes the first switch to execute a first auto-MLAG module that determines the first system information; and

causes the second switch to execute a second auto-M LAG module that determines the second system information.

19. One or more non-transitory computer-readable storage media including instructions that, when executed by one or more processors, cause the one or more processors to perform steps of:

receiving a first discovery packet via a first uplink port associated with a first switch that is included in a multi-chassis link aggregation group (MLAG);

determining that first system information associated with the MLAG matches second system information associated with the MLAG and included in the first discovery packet; and

in response to the determining, concluding that the first uplink port is included in an inter-peer link connecting the first switch to a second switch that is included in the MLAG.

20. A system, comprising:

a memory that includes instructions; and

a processor that is coupled to the memory and, when executing the instructions:

receives a first discovery packet via a first uplink port associated with a first switch that is included in a multi-chassis link aggregation group (MLAG);

determines that first system information associated with the MLAG matches second system information associated with the MLAG and included in the first discovery packet;

in response to the determining, concludes that the first uplink port is included in an inter-peer link connecting the first switch to a second switch that is included in the MLAG.

Assignments (2)
SECURITY INTEREST Recorded Jan 20, 2026
From: SUPER MICRO COMPUTER, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 074447/0643 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2020
From: JAILANI, SAHUL HAMEED ABDUL KADER
To: SUPER MICRO COMPUTER, INC.
Reel/Frame 051951/0088 →
Continuity (3)
Continuation 15265719 · Sep 14, 2016
Provisional Application 62325926 · Apr 21, 2016
Related Publication 20200119990A1 · Apr 16, 2020