Procedure for reviewing an FPGA-program

1. A method for detecting errors of a field-programmable gate array (FPGA), comprising:

testing, by a monitoring program executed on a processor in communication with the FPGA, communication between the FPGA and a further FPGA, wherein testing the communication between the FPGA and the further FPGA comprises:

obtaining, by the monitoring program executed on the processor, a signal value from the FPGA prior to transmission of the signal value from the FPGA to the further FPGA;

obtaining, by the monitoring program executed on the processor, a reference value from the further FPGA after transmission of the signal value from the FPGA to the further FPGA; and

comparing, by the monitoring program executed on the processor, the signal value from the FPGA to the reference value from the further FPGA in order to detect whether an error has occurred in the communication between the FPGA and the further FPGA, wherein the signal value and the reference value are different, and wherein the monitoring program detects that an error has occurred in the communication between the FPGA and the further FPGA in response to determining that the reference value does not correspond to the signal value being changed by the further FPGA in a known manner.

2. A method for detecting errors of a first field-programmable gate array (FPGA) program, comprising:

receiving, by a monitoring program executed on a processor connected to an FPGA on which the first FPGA program is executed, a signal value read out from the first FPGA program; and

comparing, by the monitoring program executed on the processor, the signal value to a reference value from a source other than the first FPGA program in order to detect errors of the first FPGA program;

wherein a plurality of comparisons between signal values and reference values are performed and combined;

wherein respective signal values are compared to reference values more frequently based on memory locations and/or logic elements corresponding to the respective signal values being exposed to a higher thermal load relative to other signal values corresponding to memory locations and/or logic elements exposed to a lower thermal load.

3. The method as recited in claim 2 , wherein the reference value is a predefined value.

4. The method as recited in claim 2 , wherein the signal value and the reference value each specify a memory address in a BlockRAM of the FPGA.

5. The method as recited in claim 2 , wherein an error of the first FPGA program is detected based on the signal value being greater than a first reference value and/or less than a second reference value.

6. The method as recited in claim 2 , wherein the reference value is set after a write access to a BlockRAM of the FPGA.

7. The method as recited in claim 4 , wherein the BlockRAM is divided into a plurality of partitions, and at least one reference value is used for each partition.

8. The method as recited in claim 2 , wherein the reference value is dynamically generated in the processor.

9. The method as recited in claim 2 , wherein the monitoring program sends a stimulation value to the FPGA.

10. The method as recited in claim 9 , wherein the stimulation value overwrites a constant in the first FPGA program.

11. The method as recited in claim 1 , wherein the signal value is read out from the FPGA via readback.

12. A system, comprising:

a processor configured to execute a monitoring program; and

a field-programmable gate array (FPGA) in communication with the processor; and

a further FPGA in communication with the processor;

wherein the first FPGA program is configured to transmit a signal value to the further FPGA; and

wherein the monitoring program is configured to test communication between the FPGA and the further FPGA, wherein testing the communication between the FPGA and the further FPGA comprises:

obtaining a signal value from the FPGA prior to transmission of the signal value from the FPGA to the further FPGA;

obtaining a reference value from the further FPGA after transmission of the signal value from the FPGA to the further FPGA; and

comparing the signal value from the FPGA to the reference value from the further FPGA in order to detect whether an error has occurred in the communication between the FPGA and the further FPGA, wherein the signal value and the reference value are different, and wherein the monitoring program detects that an error has occurred in the communication between the FPGA and the further FPGA in response to determining that the reference value does not correspond to the signal value being changed by the further FPGA in a known manner.

13. The method as recited in claim 2 , wherein thermal load on memory locations is estimated via simulation.

14. The method as recited in claim 2 , wherein the signal value is read out from the first FPGA program via readback.