Method and system for ripple suppression in multi-phase buck converters
Methods and systems for ripple suppression in multi-phase buck converters may comprise a buck converter for providing an output DC voltage with controlled ripple current. The buck converter may include one or more main buck converter stages with coupled outputs and one or more harmonic suppression buck converter stages in parallel with the one or more main buck converter stages. The one or more suppression buck converter stages may provide suppression currents at the coupled outputs to cancel ripple currents generated in the one or main buck converter stages. Each of the one or more main buck converter stages and each of the one or more suppression buck converter stages may include a stacked transistor pair with an inductor at an output. A drain terminal of one transistor of each transistor pair in the one or more main buck converter stages may be biased at a first supply voltage.
1. A system for power control, the system comprising:
a buck converter for providing an output DC voltage with controlled ripple current, the buck converter comprising:
one or more main buck converter stages with coupled outputs;
one or more harmonic suppression buck converter stages in parallel with the one or more main buck converter stages, the one or more suppression buck converter stages being operable to provide suppression currents at the coupled outputs to cancel ripple currents generated in the one or more main buck converter stages, wherein each of the one or more main buck converter stages and each of the one or more suppression buck converter stages comprises a stacked transistor pair with an inductor at an output; and
a supply voltage buck converter that is biased by a first supply voltage, wherein a drain terminal of one transistor of each transistor pair in the one or more suppression buck converter stages is biased at a second supply voltage, wherein the second supply voltage is generated by a supply voltage buck converter that is biased by the first supply voltage.
2. The system of claim 1 , wherein a drain terminal of one transistor of each transistor pair in the one or more main buck converter stages is biased at a first supply voltage.
3. The system of claim 1 , wherein the first supply voltage is equal to the second supply voltage.
4. The system of claim 1 , wherein the second voltage is less than the first supply voltage.
5. The system of claim 1 , wherein the second voltage configures the suppression currents.
6. The system of claim 1 , wherein the inductances in the one or more harmonic suppression buck stages are different for each stage.
7. The system of claim 1 , wherein the inductances in the one or more harmonic suppression buck stages are configurable.
8. A method for power control, comprising:
in a buck converter comprising one or more main buck converter stages with coupled outputs and one or more harmonic suppression buck converter stages in parallel with the one or more main buck converter stages:
providing an output DC voltage with controlled ripple current, wherein the one or more suppression buck converter stages provides suppression currents at the coupled outputs to cancel ripple currents generated in the one or main buck converters stages wherein each of the one or more main buck converter stages and each of the one or more suppression buck converter stages comprises a stacked transistor pair with an inductor at an output;
generating a second supply voltage using a supply voltage buck converter that is biased by a first supply voltage; and
biasing a drain terminal of one transistor of each transistor pair in the one or more suppression buck converter stages at the second supply voltage.
9. The method of claim 8 , comprising biasing a drain terminal of one transistor of each transistor pair in the one or more main buck converter stages at a first supply voltage.
10. The method of claim 8 , wherein the second voltage is less than the first supply voltage.
11. The method of claim 8 , wherein the first supply voltage is equal to the second supply voltage.
12. The method of claim 8 , wherein the second voltage configures the suppression currents.
13. The method of claim 8 , wherein the inductances in the one or more harmonic suppression buck stages are different for each stage and/or are configurable.
14. A system for power control, the system comprising:
a buck converter for providing an output DC voltage with controlled ripple current, the buck converter comprising:
one or more main buck converter stages with coupled outputs;
a harmonic suppression digital-to-analog-converter (DAC) in parallel with the one or more main buck converter stages, the harmonic suppression DAC being operable to provide suppression current at the coupled outputs to cancel ripple currents generated in the one or main buck converter stages, wherein each of the one or more main buck converter stages and the harmonic suppression DAC comprises a stacked transistor pair with an inductor at an output; and
a supply voltage buck converter that is biased by a first supply voltage, wherein a drain terminal of one transistor of each transistor pair in the one or more buck converter stages is biased at a second supply voltage, wherein the second supply voltage is generated by a supply voltage buck converter that is biased by the first supply voltage.