SILICON CARBIDE TRENCH POWER DEVICE
A power semiconductor device includes a substrate having a body region and a drift layer; a trench formed in the substrate; a gate dielectric structure including a first gate insulation layer having a first dielectric constant and a second gate insulation layer having a second dielectric constant different from the first dielectric constant; and a conductive material provided within the trench over the gate dielectric structure.
1 . A power semiconductor device, comprising:
a substrate having a body region and a drift layer;
a trench formed in the substrate;
a gate dielectric structure including a first gate insulation layer having a first dielectric constant and a second gate insulation layer having a second dielectric constant different from the first dielectric constant; and
a conductive material provided within the trench over the gate dielectric structure.
2 . The power device of claim 1 , wherein the substrate is a silicon carbide substrate, and the first gate insulation layer is provided over a sidewall of the trench and the second gate insulation layer is provided over a bottom of the trench.
3 . The power device of claim 2 , wherein the first gate insulation layer includes silicon oxide, and the second gate insulation layer includes dielectric material having a dielectric constant higher than that of the silicon oxide.
4 . The power device of claim 3 , wherein the second gate insulation layer includes silicon nitride.
5 . The power device of claim 3 , wherein the second gate insulation layer includes aluminum nitride.
6 . The power device of claim 1 , wherein the substrate is a silicon carbide substrate, and the first gate insulation layer extends below the body region and into the drift layer.
7 . The power device of claim 1 , wherein the first gate insulation layer includes silicon oxide, and the second gate insulation layer includes dielectric material having a dielectric constant greater than that of the silicon oxide, the second gate insulation layer being configured to reduce electric field buildup in the trench during an operation of the power device.
8 . The power device of claim 7 , wherein the second gate insulation layer includes a lower portion and a side portion that wrap a bottom corner of the conductive material provided in the trench, the side potion being configured to reduce electric field buildup at the bottom corner during the power device operation.
9 . The power device of claim 8 , wherein the side portion of the second gate insulation layer has a height of at least 0.05 um.
10 . The power device of claim 7 , further comprising:
a compensation region provided below the trench in the drift layer, the compensation region having a conductivity opposite to that of the drift layer.
11 . A method for fabricating a power semiconductor device, the method comprising:
etching a trench in a substrate having a body region and a drift layer;
depositing a first dielectric material over the substrate and into the trench, the first dielectric material having a first dielectric constant;
etching the first dielectric material to expose a sidewall of the trench and provide the first dielectric material with a first thickness;
forming a second dielectric material over the sidewall of the trench, the second dielectric material having a second dielectric constant different from the first dielectric constant; and
providing a conductive material within the trench and over the first and second dielectric materials to from a gate,
wherein the first and second dielectric materials form a gate dielectric structure for the gate.
12 . The method of claim 11 , wherein the substrate is a silicon carbide substrate, the method further comprising:
etching the first dielectric material to reduce the first dielectric material to a second thickness.
13 . The method of claim 12 , wherein the first dielectric material is provided with a lower portion and a side portion that wrap a bottom corner of the conductive material.
14 . The method of claim 12 , wherein the first dielectric material has a dielectric constant of at least 4 , and the second dielectric material is silicon oxide.
15 . The method of claim 14 , wherein the first gate dielectric material includes silicon nitride.
16 . The method of claim 14 , wherein the first gate dielectric material includes aluminum nitride.
17 . The method of claim 12 , further comprising:
forming a compensation region below the trench in the drift layer, the compensation region having a conductivity that is opposite to that of the drift layer.
18 . A method for fabricating a power semiconductor device, the method comprising:
etching a trench in a substrate having a body region and a drift layer; and
forming a gate dielectric structure including a first gate insulation layer having a first dielectric constant and a second gate insulation layer having a second dielectric constant that is different from the first dielectric constant; and
providing a conductive material within the trench and over the gate dielectric structure to make a gate.
19 . The method of claim 18 , wherein the substrate is a silicon carbide substrate, the first gate insulation layer includes silicon oxide, and the second gate insulation layer includes silicon nitride or aluminum nitride.
20 . The method of claim 18 , wherein the second gate insulation layer wraps around a bottom corner of the conductive material to reduce electric field buildup at the bottom corner during an operation of the power device.