Semiconductor power device and method for manufacture
A device includes a first doped semiconductor region and a second oppositely doped semiconductor region that are separated by an undoped or lightly-doped semiconductor drift region. The device further includes a first electrode structure making an ohmic contact with the first doped semiconductor region, and a second electrode structure making a universal contact with the second doped semiconductor region. The universal contact of the second electrode structure allows flow of both electrons and holes into, and out of, the device.
1. A device comprising:
a first doped semiconductor layer and a second oppositely doped semiconductor layer that are separated by a semiconductor drift region;
and
an electrode structure making a universal contact with the second oppositely doped semiconductor layer the universal contact allowing flow of both electrons and holes, the electrode structure including at least one doped semiconductor region of a first conductivity type and at least one semiconductor region of a second conductivity in contact with the second oppositely doped semiconductor layer, the electrode structure further including an oxide layer disposed between the at least one doped semiconductor region of the first conductivity type and a metal or metal alloy layer.
2. The device of claim 1 , wherein the at least one doped semiconductor region of the first conductivity type includes at least one P+ doped semiconductor region and the at least one semiconductor region of the second conductivity includes at least one N+ doped semiconductor region.
3. The device of claim 2 , wherein the at least one P+ doped semiconductor region and the at least one N+ doped semiconductor region are disposed between the metal or metal alloy layer and the second oppositely doped semiconductor layer.
4. The device of claim 3 , wherein the electrode structure includes a plurality of P+ doped semiconductor regions alternating with a plurality of N+ doped semiconductor regions disposed between the metal or metal alloy layer and the second oppositely doped semiconductor layer.
5. The device of claim 1 , wherein at least one P+ doped semiconductor region has a first area of contact with the second oppositely doped semiconductor layer, and at least one N+ doped semiconductor region has a second area of contact with the second oppositely doped semiconductor layer, a ratio of the first area and the second area forming a P-to-N areal ratio of the universal contact.
6. The device of claim 5 , wherein the P-to-N areal ratio determines a reverse current recovery time of the device.
7. The device of claim 5 , wherein the P-to-N areal ratio determines a forward current of the device.
8. The device of claim 5 , wherein the P-to-N areal ratio is between 0.2:1 and 5:1.
9. The device of claim 1 , wherein the first doped semiconductor layer is a P-doped semiconductor region, the second oppositely doped semiconductor layer is an N-type semiconductor substrate region having a resistivity in a range of 0.001 to 50 Ω-cm, and the semiconductor drift region is an N-type epitaxial semiconductor region having a resistivity in a range of 20 to 200 Ω-cm.
10. The device of claim 9 , wherein the first doped semiconductor layer includes a P+ layer formed on a top surface of an N-type epitaxial layer and a metal layer deposited on the P+ layer.
11. A device comprising:
a doped semiconductor region in contact with a semiconductor drift region;
and
an electrode structure including an alternating array of P+ doped semiconductor regions and N+ doped semiconductor regions in contact with the second doped semiconductor region, the electrode structure including an oxide layer disposed between a metal layer and the alternating array of the P+ doped semiconductor regions and the N+ doped semiconductor regions.
12. The device of claim 11 , wherein the oxide layer covers the P+ doped semiconductor regions and extends partially over the N+ doped semiconductor regions of the alternating array.
13. A device comprising:
an epitaxial semiconductor layer disposed on a semiconductor substrate; and
a universal contact structure disposed on a back surface of the semiconductor substrate,
the universal contact structure including photolithographically patterned and implanted regions of a first conductivity type and a second conductivity type disposed on the back surface of the semiconductor substrate, the regions of the first conductivity type and the second conductivity type including laser annealed dopants, and a patterned oxide layer disposed over the regions of the first conductivity type and partially over the regions of the second conductivity type.
14. The device of claim 13 , wherein the regions of the first conductivity type and the second conductivity type include photolithographically patterned and implanted P+ regions and N+ regions disposed on the back surface of the semiconductor substrate, the P+ regions including laser annealed p-dopants and the N+ regions including laser annealed n-dopants.
15. The device of claim 13 , wherein a back metal is disposed over the oxide layer.
16. The device of claim 13 , wherein the semiconductor substrate is a N-type semiconductor substrate having a resistivity in a range of 0.01 to 10 Ω-cm, and the epitaxial semiconductor layer is a N-type epitaxial layer has having a resistivity in a range of 20 to 200 Ω-cm.
17. The device of claim 16 , further comprising: a P+ layer formed on a top surface of the N-type epitaxial layer; and
a metal layer disposed on the P+ layer.
18. The device of claim 17 , wherein the P+ layer includes p dopant species thermally diffused, and/or implanted, into the top surface of the n-type epitaxial layer.