IP Library Granted Patent US 11,428,826
Granted Patent B2
US 11,428,826 · App. 16/670,527 · Granted Aug 30, 2022

Silicon photomultipliers with split microcells

Inventor: Brian Patrick McGarvey (Templemartin, IE)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
G01T1/248G01T1/247H01L27/1463H01L27/14636H01L27/14658H01L31/02027H01L31/107
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Quick Facts
Patent No.
US 11,428,826
App. No.
16/670,527
Granted
Aug 30, 2022
Kind
B2
Abstract

A semiconductor device may include a plurality of single-photon avalanche diodes. The single-photon avalanche diodes may be arranged in microcells. Each microcell may be a split microcell with first and second independent microcell segments. Each microcell segment in the split microcell may have a respective single-photon avalanche diode that is coupled to an output line. The single-photon avalanche diode of each microcell segment may also be coupled to a respective resistor that is used to quench avalanches in the single-photon avalanche diode. Splitting the microcell may reduce the recovery time of each microcell. The segments of the split microcell may be positioned close together, even if susceptible to optical crosstalk. Intra-microcell isolation structures may be formed between the microcell segments. Inter-microcell isolation structures may be formed around a perimeter of the split microcell. The intra-microcell and inter-microcell isolation structures may be different.

Claims (40)

1. A semiconductor device comprising:

a substrate;

a plurality of microcells in the substrate, wherein each one of the microcells comprises first and second single-photon avalanche diodes separated by intra-microcell isolation structures; and

inter-microcell isolation structures formed between the adjacent microcells.

2. The semiconductor device defined in claim 1 , wherein the intra-microcell isolation structures are different than the inter-microcell isolation structures.

3. The semiconductor device defined in claim 2 , wherein the inter-microcell isolation structures comprise deep trench isolation structures and wherein the intra-microcell isolation structures do not include any deep trench isolation structures.

4. The semiconductor device defined in claim 2 , wherein the inter-microcell isolation structures comprise local oxidation of silicon structures and polysilicon-filled trenches.

5. The semiconductor device defined in claim 4 , wherein the intra-microcell isolation structures comprise local oxidation of silicon structures and wherein the intra-microcell isolation structures do not include polysilicon-filled trenches.

6. The semiconductor device defined in claim 1 , wherein each one of the microcells comprises:

a first electrical connection between the first single-photon avalanche diode and a first output line; and

a second electrical connection between the second single-photon avalanche diode and a second output line.

7. The semiconductor device defined in claim 6 , wherein the first electrical connection is between a first anode of the first single-photon avalanche diode and the first output line and wherein the second electrical connection is between a second anode of the second single-photon avalanche diode and the second output line.

8. The semiconductor device defined in claim 1 , wherein each one of the microcells comprises:

a first resistor;

a second resistor;

a first electrical connection between the first single-photon avalanche diode and the first resistor; and

a second electrical connection between the second single-photon avalanche diode and the second resistor.

9. The semiconductor device defined in claim 8 , wherein the first electrical connection is between a first cathode of the first single-photon avalanche diode and the first resistor and wherein the second electrical connection is between a second cathode of the second single-photon avalanche diode and the second resistor.

10. A silicon photomultiplier comprising:

a semiconductor substrate; and

an array of microcells in the semiconductor substrate, wherein at least one microcell of the array of microcells is a split microcell with first and second microcell segments and wherein a crosstalk probability between the first and second microcell segments is greater than 90%.

11. The silicon photomultiplier defined in claim 10 , wherein the first and second microcell segments of the split microcell are separated by a distance that is less than two microns.

12. The silicon photomultiplier defined in claim 10 , wherein the first microcell segment includes a first single-photon avalanche diode and wherein the second microcell segment includes a second single-photon avalanche diode.

13. The silicon photomultiplier defined in claim 12 , wherein the split microcell further comprises:

a first resistor;

a second resistor;

a first contact between the first single-photon avalanche diode and the first resistor; and

a second contact between the second single-photon avalanche diode and the second resistor.

14. The silicon photomultiplier defined in claim 10 , wherein the split microcell further comprises:

a first contact between the first microcell segment and a first output line; and

a second contact between the second microcell segment and a second output line.

15. The silicon photomultiplier defined in claim 10 , further comprising:

trench isolation structures formed around a perimeter of the split microcell.

16. The silicon photomultiplier defined in claim 15 , further comprising:

isolation structures that are different than the trench isolation structures and that are formed between the first and second microcell segments of the split microcell.

17. A semiconductor device comprising:

a substrate;

a plurality of single-photon avalanche diodes in the substrate;

first isolation structures that surround pairs of single-photon avalanche diodes; and

second isolation structures formed between the single-photon avalanche diodes of each of the pairs of single-photon avalanche diodes, wherein a crosstalk probability between the single-photon avalanche diodes of each of the pairs of single-photon avalanche diodes is greater than 90%, wherein the second isolation structures are different than the first isolation structures and wherein the first isolation structures comprise deep trench isolation structures.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 054090, FRAME 0617 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064081/0167 →
SECURITY INTEREST Recorded Oct 16, 2020
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION; ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 054090/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 31, 2019
From: MCGARVEY, BRIAN PATRICK
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 050900/0182 →
Continuity (2)
Provisional Application 62897649 · Sep 9, 2019
Related Publication 20210072411A1 · Mar 11, 2021
Cited By (1)
US 12,309,501