IP Library Granted Patent US 10,997,019
Granted Patent B1
US 10,997,019 · App. 16/670,680 · Granted May 4, 2021

System and method for facilitating high-capacity system memory adaptive to high-error-rate and low-endurance media

Inventor: Shu Li (Bothell, WA)
Assignee: Alibaba Group Holding Limited
G06F11/1044G06F11/073G06F11/1068G06F11/1072G06F12/0207G06F2212/7201
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Quick Facts
Patent No.
US 10,997,019
App. No.
16/670,680
Granted
May 4, 2021
Kind
B1
Abstract

The system receives a request to write a first piece of data to a non-volatile memory. The system encodes, based on an error correction code (ECC), the first piece of data to obtain a first ECC codeword which includes a plurality of ordered parts and a first parity. The system writes the plurality of ordered parts in multiple rows. The system writes the first parity to a same row in which a starting ordered part is written. The system updates, in a data structure, entries associated with the ordered parts. A respective entry indicates: a virtual address associated with a respective ordered part, a physical address at which the respective ordered part is written, and an index corresponding to a virtual address associated with a next ordered part. A first entry associated with the starting ordered part further indicates a physical address at which the first parity is written.

Claims (102)

1. A computer-implemented method, comprising:

receiving a request to write a first piece of data to a non-volatile memory;

encoding, based on an error correction code (ECC), the first piece of data to obtain a first ECC codeword which includes a plurality of ordered parts and a first parity;

writing the plurality of ordered parts in multiple rows of the non-volatile memory;

writing the first parity to a same row in which a starting ordered part is written; and

updating, in a data structure, entries associated with the ordered parts;

wherein a respective entry indicates: a virtual address associated with a respective ordered part, a physical address at which the respective ordered part is written, and an index corresponding to a virtual address associated with a next ordered part; and

wherein a first entry associated with the starting ordered part further indicates a physical address at which the first parity is written.

2. The method of claim 1 , wherein writing the plurality of ordered parts comprises:

determining that at least one of the plurality of ordered parts comprises updated data associated with former data previously written to a first row of the multiple rows;

writing the at least one of the plurality of ordered parts directly to a same physical location at which the former data is previously written; and

refraining from copying out any valid parts of the first row to a new row.

3. The method of claim 1 , wherein writing the first parity to the same row in which the first ordered part is written comprises:

replacing a former parity in the same row.

4. The method of claim 1 , wherein virtual addresses associated with the ordered parts of the first piece of data are not consecutive.

5. The method of claim 1 , further comprising:

receiving a request to write a second piece of data to the non-volatile memory; and

writing the second piece of data to the non-volatile memory,

wherein the second piece of data comprises updated data associated with former data previously written to the non-volatile memory, and

wherein the second piece of data comprises a plurality of parts.

6. The method of claim 5 , wherein writing the second piece of data comprises:

marking the former data as expired;

identifying a first row with a number of valid parts less than a predetermined number;

writing a third piece of data to a new row, wherein the third piece of data comprises the valid parts of the identified first row and the plurality of parts of the second piece of data;

encoding, based on the error correction code (ECC), the third piece of data to obtain a second ECC codeword which includes a second parity; and

writing the second parity to the new row.

7. The method of claim 1 , further comprising:

receiving a request to read a portion of the first piece of data from the non-volatile memory;

obtaining the plurality of ordered parts of the first piece of data from the non-volatile memory by searching the data structure based on an initial virtual address for a respective ordered part associated with the portion of the first piece of data and for the first entry;

obtaining, from the first entry, the first parity based on the physical address at which the first parity is written;

processing the obtained plurality of ordered parts and the obtained first parity to obtain the first ECC codeword;

decoding, based on the error correction code (ECC), the first ECC codeword to obtain the first piece of data; and

returning the requested portion of the first piece of data.

8. The method of claim 7 , wherein processing the obtained plurality of ordered parts and the obtained first parity to obtain the first ECC codeword comprises:

truncating, from the first entry, the physical address at which the starting ordered part is written to obtain the physical address at which the first parity is written;

reshuffling the plurality of ordered parts and the obtained first parity; and

concatenating the reshuffled plurality of ordered parts and the obtained first parity to obtain the first ECC codeword.

9. The method of claim 7 , wherein obtaining the plurality of ordered parts of the first piece of data from the non-volatile memory comprises:

determining an initial virtual address for a respective ordered part associated with the portion of the first piece of data;

performing, in the data structure, a first search for an initial entry based on the initial virtual address,

wherein the initial entry indicates: a first physical address at which the respective ordered part is written, and a first index corresponding to a virtual address associated with a next ordered part;

reading the respective ordered part from the first physical address; and

performing, in the data structure, a second search for a next entry based on the first index to obtain a second physical address at which the next ordered part is written and from which to read the next ordered part.

10. The method of claim 7 , wherein obtaining the first parity from the first entry further comprises:

calculating the physical address at which the first parity is written by truncating the physical address at which the starting ordered part is written.

11. A computer system, comprising:

a processor; and

a memory coupled to the processor and storing instructions, which when executed by the processor cause the processor to perform a method, the method comprising:

receiving a request to write a first piece of data to a non-volatile memory;

encoding, based on an error correction code (ECC), the first piece of data to obtain a first ECC codeword which includes a plurality of ordered parts and a first parity;

writing the plurality of ordered parts in multiple rows of the non-volatile memory;

writing the first parity to a same row in which a starting ordered part is written; and

updating, in a data structure, entries associated with the ordered parts;

wherein a respective entry indicates: a virtual address associated with a respective ordered part, a physical address at which the respective ordered part is written, and an index corresponding to a virtual address associated with a next ordered part; and

wherein a first entry associated with the starting ordered part further indicates a physical address at which the first parity is written.

12. The computer system of claim 11 , wherein writing the plurality of ordered parts comprises:

determining that at least one of the plurality of ordered parts comprises updated data associated with former data previously written to a first row of the multiple rows;

writing the at least one of the plurality of ordered parts directly to a same physical location at which the former data is previously written; and

refraining from copying out any valid parts of the first row to a new row.

13. The computer system of claim 11 , wherein writing the first parity to the same row in which the first ordered part is written comprises:

replacing a former parity in the same row.

14. The computer system of claim 11 , wherein virtual addresses associated with the ordered parts of the first piece of data are not consecutive.

15. The computer system of claim 11 , wherein the method further comprises:

receiving a request to write a second piece of data to the non-volatile memory; and

writing the second piece of data to the non-volatile memory,

wherein the second piece of data comprises updated data associated with former data previously written to the non-volatile memory, and

wherein the second piece of data comprises a plurality of parts.

16. The computer system of claim 15 , wherein writing the second piece of data comprises:

marking the former data as expired;

identifying a first row with a number of valid parts less than a predetermined number;

writing a third piece of data to a new row, wherein the third piece of data comprises the valid parts of the identified first row and the plurality of parts of the second piece of data;

encoding, based on the error correction code (ECC), the third piece of data to obtain a second ECC codeword which includes a second parity; and

writing the second parity to the new row.

17. The computer system of claim 11 , wherein the method further comprises:

receiving a request to read a portion of the first piece of data from the non-volatile memory;

obtaining the plurality of ordered parts of the first piece of data from the non-volatile memory by searching the data structure based on an initial virtual address for a respective ordered part associated with the portion of the first piece of data and for the first entry;

obtaining, from the first entry, the first parity based on the physical address at which the first parity is written;

processing the obtained plurality of ordered parts and the obtained first parity to obtain the first ECC codeword;

decoding, based on the error correction code (ECC), the first ECC codeword to obtain the first piece of data; and

returning the requested portion of the first piece of data.

18. The computer system of claim 17 , wherein processing the obtained plurality of ordered parts and the obtained first parity to obtain the first ECC codeword comprises:

truncating, from the first entry, the physical address at which the starting ordered part is written to obtain the physical address at which the first parity is written;

reshuffling the plurality of ordered parts and the obtained first parity; and

concatenating the reshuffled plurality of ordered parts and the obtained first parity to obtain the first ECC codeword.

19. The computer system of claim 17 , wherein obtaining the plurality of ordered parts of the first piece of data from the non-volatile memory comprises:

determining an initial virtual address for a respective ordered part associated with the portion of the first piece of data;

performing, in the data structure, a first search for an initial entry based on the initial virtual address,

wherein the initial entry indicates: a first physical address at which the respective ordered part is written, and a first index corresponding to a virtual address associated with a next ordered part;

reading the respective ordered part from the first physical address; and

performing, in the data structure, a second search for a next entry based on the first index to obtain a second physical address at which the next ordered part is written and from which to read the next ordered part.

20. An apparatus, comprising:

a controller unit, which comprises a first interface for communicating with a host, a second interface for communicating with a volatile memory, a third interface for communicating via a memory channel with a non-volatile memory, a bridge module, and a backend module;

the volatile memory; and

the non-volatile memory;

wherein the controller unit is configured to:

receive, via the first interface, a request to write a first piece of data to the non-volatile memory;

encode, by the backend module based on an error correction code (ECC), the first piece of data to obtain a first ECC codeword which includes a plurality of ordered parts and a first parity;

write, via the third interface, the plurality of ordered parts in multiple rows of the non-volatile memory;

write, via the third interface, the first parity to a same row in which a starting ordered part is written; and

update, by the bridge module in a data structure, entries associated with the ordered parts;

wherein a respective entry indicates: a virtual address associated with a respective ordered part, a physical address at which the respective ordered part is written, and an index corresponding to a virtual address associated with a next ordered part; and

wherein a first entry associated with the starting ordered part further indicates a physical address at which the first parity is written.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2026
From: ALIBABA GROUP HOLDING LIMITED
To: CLOUD INTELLIGENCE ASSETS HOLDING (SINGAPORE) PRIVATE LIMITED
Reel/Frame 075499/0384 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2019
From: LI, SHU
To: ALIBABA GROUP HOLDING LIMITED
Reel/Frame 050894/0967 →
Cited By (1)
US 1,073,701