Static random-access memory (SRAM) compute in-memory integration
Certain aspects provide methods and apparatus for in-memory convolution computation. An example circuit for such computation generally includes a memory cell having a bit-line and a complementary bit-line and a computation circuit coupled to a computation input node of the circuit and at least one of the bit-line or the complementary bit-line. In certain aspects, the computation circuit comprises a counter, an NMOS transistor coupled to the memory cell, and a PMOS transistor coupled to the memory cell, drains of the NMOS and PMOS transistors being coupled to the counter.
1. A circuit for in-memory computation, comprising:
a memory cell having a bit-line and a complementary bit-line; and
a computation circuit coupled to a computation input node of the circuit and at least one of the bit-line or the complementary bit-line, wherein:
the computation circuit comprises a counter, a first n-type metal-oxide-semiconductor (NMOS) transistor coupled to the memory cell, and a first p-type metal-oxide-semiconductor (PMOS) transistor coupled to the memory cell, drains of the first NMOS and PMOS transistors being coupled to the counter;
a gate of the first NMOS transistor is connected with the computation input node;
a gate of the first PMOS transistor is coupled to the computation input node;
a source of the first NMOS transistor is coupled to the bit-line; and
a source of the first PMOS transistor is coupled to the complementary bit-line.
2. The circuit of claim 1 , wherein the computation circuit is configured to perform an exclusive NOR (XNOR) or exclusive OR (XOR) operation.
3. The circuit of claim 1 , wherein the computation circuit further comprises a second PMOS transistor having a source coupled to the drain of the first NMOS transistor and having a drain coupled to the source of the first NMOS transistor.
4. The circuit of claim 3 , wherein the computation circuit further comprises a second NMOS transistor having a source coupled to the drain of the first PMOS transistor and having a drain coupled to the source of the first PMOS transistor.
5. A circuit for in-memory computation, comprising:
a memory cell having a bit-line and a complementary bit-line;
a computation circuit coupled to a computation input node of the circuit and at least one of the bit-line or the complementary bit-line, wherein the computation circuit comprises a counter, a first n-type metal-oxide-semiconductor (NMOS) transistor coupled to the memory cell, and a first p-type metal-oxide-semiconductor (PMOS) transistor coupled to the memory cell, drains of the first NMOS and PMOS transistors being coupled to the counter; and
an enable circuit having:
a second NMOS transistor coupled between the computation input node and the first NMOS transistor, a gate of the second NMOS transistor being coupled to an enable input node; and
a second PMOS transistor coupled between a complementary computation input node and the first PMOS transistor, a gate of the second PMOS transistor being coupled to a complementary enable input node.
6. A circuit for in-memory computation, comprising:
a memory cell having a bit-line and a complementary bit-line;
a computation circuit coupled to a computation input node of the circuit and at least one of the bit-line or the complementary bit-line, wherein the computation circuit comprises a counter, a first n-type metal-oxide-semiconductor (NMOS) transistor coupled to the memory cell, and a first p-type metal-oxide-semiconductor (PMOS) transistor coupled to the memory cell, drains of the first NMOS and PMOS transistors being coupled to the counter, and wherein a gate of the first NMOS transistor is connected with the computation input node; and
an enable circuit having a second NMOS transistor coupled between the counter and the drains of the first NMOS transistor and the first PMOS transistor, a gate of the second NMOS transistor being coupled to an enable input node.
7. The circuit of claim 6 , wherein the enable circuit further comprises a second PMOS transistor having a source coupled to a drain of the second NMOS transistor and a drain coupled to a source of the second NMOS transistor, a gate of the second PMOS transistor being coupled to a complementary enable input node.
8. The circuit of claim 1 , wherein the memory cell is one of a plurality of memory cells of a static random-access memory (SRAM).
9. The circuit of claim 1 , further comprising a transition assist circuit coupled to at least one of the bit-line or the complementary bit-line, the transition assist circuit comprising:
a first inverter; and
a second inverter, an output of the first inverter being coupled to an input of the second inverter and an output of the second inverter being coupled to an input of the first inverter.
10. The circuit of claim 1 , further comprising an enable circuit having:
a second NMOS transistor coupled between the computation input node and the first NMOS transistor, a gate of the second NMOS transistor being coupled to an enable input node; and
a second PMOS transistor coupled between a complementary computation input node and the first PMOS transistor, a gate of the second PMOS transistor being coupled to a complementary enable input node.
11. The circuit of claim 5 , wherein at least one of a gate of the first NMOS transistor or a gate of the first PMOS transistor is coupled to the computation input node.
12. The circuit of claim 11 , wherein a source of the first NMOS transistor is coupled to the bit-line, and wherein a source of the first PMOS transistor is coupled to the complementary bit-line.