Motor driver with multipurpose pin

1. A motor driver system, comprising:

a motor driver configured to couple with a motor, the motor driver comprising a multipurpose pin;

wherein the motor driver is configured to couple with a controller through at least the multipurpose pin;

wherein the motor driver, during an enable mode, is configured to receive serial data from the controller and to send serial data to the controller using the multipurpose pin during a normal operation mode of the motor driver; and

wherein the motor driver is configured to output a frequency generator (FG) signal to the controller using the multipurpose pin during the normal operation mode of the motor driver.

2. The system of claim 1 , wherein the motor driver, at an end of the enable mode, is configured to wait during a synchronization period before terminating one of sending serial data to or receiving serial data from the controller.

3. The system of claim 1 , wherein the motor driver further comprises:

an interface comprising:

a communication controller, an edge detector, and a busy signal generator operatively coupled together and coupled with an inverter, the inverter coupled with the multipurpose pin; and

a selection signal generator.

4. The system of claim 3 , wherein the selection signal generator comprises:

a first inverter coupled with an output of a frequency generator logic unit;

a second inverter coupled with the output of the busy signal generator;

a first not-AND (NAND) gate having a first input coupled with an output of the first inverter and a second input coupled to an output of the second inverter;

a first AND gate having a first input coupled to an output of the first NAND gate and a second input coupled to an output of an enable signal generator;

a second AND gate having a first input coupled to the output of the busy signal generator and a second input coupled to the output of the enable signal generator;

a multiplexer having a first input coupled to the output of the first AND gate, a second input coupled to the output of the second AND gate, and a control input;

a flip-flop coupled to the output of the multiplexer and to an output coupled with the control input, the flip-flop configured to generate a selection signal generator output signal in response to receiving an output signal from the multiplexer.

5. The system of claim 3 , wherein the busy signal generator comprises:

an inverter coupled with an output of the communication controller;

a first AND gate having a first input coupled with an output of the inverter and a second input coupled with an output of an enable signal generator;

a second AND gate having a first input coupled with an output of the edge detector and a second input coupled with the output of the enable signal generator;

a multiplexer coupled with an output of the first AND gate and an output of the second AND gate, the multiplexer having a control input; and

a flip-flop coupled with an output of the multiplexer, the flip-flop having an output coupled with the control input, the flip-flop configured to generate a busy signal output in response to receiving an output signal from the multiplexer.

6. The system of claim 1 , wherein the motor driver further comprises an interface comprising:

a communication controller coupled with an output of an enable signal generator, a busy signal generator, an inverter, and an edge detector;

wherein the edge detector is a positive edge detector.

7. The system of claim 6 , wherein the enable signal generator comprises:

a first inverter coupled with an output of the busy signal generator;

a second inverter coupled with an output of a selection signal generator;

a not-AND (NAND) gate comprising a first input coupled to an output of the first inverter, a second input coupled to an output of the second inverter, a third input coupled to an output of a frequency generator logic unit, and an output coupled with a multiplexer;

a third inverter comprising an input coupled to the output of the frequency generator logic unit and an output coupled with the multiplexer, the multiplexer comprising a control input and an output; and

a flip-flop comprising a data input coupled to the output of the multiplexer, and an output coupled to the control input of the multiplexer and an output of the enable signal generator, the flip-flop configured to generate an enable signal in response to receiving an output signal from the multiplexer.

8. A motor driver comprising:

a communication controller, an edge detector, an enable signal generator, a frequency generator logic unit, a selection signal generator, and a busy signal generator operatively coupled together and coupled with an inverter; and

a multipurpose pin coupled with the inverter;

wherein the motor driver is configured to couple with a controller through the multipurpose pin.

9. The system of claim 8 , wherein the motor driver, during an enable mode, is configured to receive serial data from the controller and to send serial data to the controller using the multipurpose pin during a normal operation mode of the motor driver, and

wherein the motor driver is configured to output a frequency generator (FG) signal to the controller using the multipurpose pin during the normal operation mode of the motor driver.

10. The system of claim 9 , wherein the motor driver, at an end of the enable mode, is configured to wait during a synchronization period before terminating one of sending serial data to or receiving serial data from the controller.

11. The system of claim 8 , wherein the enable signal generator comprises:

a first inverter coupled with an output of the busy signal generator;

a second inverter coupled with an output of the selection signal generator;

a not-AND (NAND) gate comprising a first input coupled to an output of the first inverter, a second input coupled to an output of the second inverter, a third input coupled to an output of the frequency generator logic unit, and an output coupled with a multiplexer;

a third inverter comprising an input coupled to the output of the frequency generator logic unit and an output coupled with the multiplexer, the multiplexer comprising a control input and an output; and

a flip-flop comprising a data input coupled to the output of the multiplexer, the flip-flop having an output coupled to the control input of the multiplexer and an output of the enable signal generator, the flip-flop configured to generate an enable signal in response to receiving an output signal from the multiplexer.

12. The system of claim 8 , wherein the selection signal generator comprises:

a first inverter coupled with an output of the frequency generator logic unit;

a second inverter coupled with the output of the busy signal generator;

a first not-AND (NAND) gate having a first input coupled with an output of the first inverter and a second input coupled to an output of the second inverter;

a first AND gate having a first input coupled to an output of the first NAND gate and a second input coupled to the output of the enable signal generator;

a second AND gate having a first input coupled to the output of the busy signal generator and a second input coupled to the output of the enable signal generator;

a multiplexer having a first input coupled to the output of the first AND gate, a second input coupled to the output of the second AND gate, and a control input;

a flip-flop coupled to the output of the multiplexer and to an output coupled with the control input, the flip-flop configured to generate a selection signal generator output signal in response to receiving an output signal from the multiplexer.

13. The system of claim 8 , wherein the busy signal generator comprises:

an inverter coupled with an output of the communication controller;

a first AND gate having a first input coupled with an output of the inverter and a second input coupled with an output of the enable signal generator;

a second AND gate having a first input coupled with an output of the edge detector and a second input coupled with the output of the enable signal generator;

a multiplexer coupled with an output of the first AND gate and an output of the second AND gate, the multiplexer having a control input; and

a flip-flop coupled with an output of the multiplexer and having an output coupled with the control input, the flip-flop configured to generate a busy signal output in response to receiving an output signal from the multiplexer.

14. A method of driving a motor, the method, comprising:

providing a motor driver configured to couple with a motor, the motor driver comprising a multipurpose pin, the multipurpose pin configured to couple a controller with the motor driver through at least the multipurpose pin;

using the motor driver, receiving serial data from the controller using the multipurpose pin and sending serial data to the controller using the multipurpose pin during a normal operation mode of the motor driver, and

outputting a frequency generator (FG) signal to the controller using the multipurpose pin during the normal operation mode of the motor driver.

15. The method of claim 14 , further comprising waiting, using the motor driver at an end of an enable mode, during a synchronization period before terminating one of sending serial data to or receiving serial data from the controller.

16. The method of claim 14 wherein receiving serial data from the controller further comprises:

beginning serial transmission of data by first setting an ENABLE signal to high, followed by simultaneously setting a BUSY signal to high, and a Selection Signal Generator Output (SELSO) to high.

17. The method of claim 14 , wherein sending serial data to the controller further comprises:

first setting a BUSY signal to low and setting a Selection Signal Generator Output (SELSO) to low while an ENABLE signal to low thereby creating a synchronization period between when serial data transmission ends and the normal operation mode of the motor driver begins.

18. The method of claim 14 , wherein an interface is coupled with the multipurpose pin where the interface is configured to sense a beginning of serial data communication to the controller and sense an ending of serial data communication to the controller; and

the interface is configured to synchronize the serial data communication with the FG signal transmitted by the multipurpose pin during the beginning and ending of serial data communication using the interface.

19. The method of claim 18 , wherein the interface comprises an edge detector configured to sense an edge of the FG signal.

20. The method of claim 19 , further comprising:

providing an output of the edge detector to a busy signal generator;

setting a BUSY signal to one of a HIGH value or a LOW value in response to the output of the edge detector using the busy signal generator; and

using the BUSY signal to create a synchronization period between when serial data transmission ends and the normal operation mode of the motor driver begins.