Semiconductor packages and related methods
View Patent ↗Methods of forming semiconductor packages include providing a first insulator layer coupled with a first metallic layer. A recess is formed in the first metallic layer and a semiconductor die is mechanically coupled therein. The die is mechanically coupled with a second metallic layer and the second metallic layer is coupled with a second insulator layer. The die and layers are at least partially encapsulated to form the semiconductor package. The first and/or second metallic layers may be insulator-metal substrates, metal-insulator-metal (MIM) substrates, or may be formed of lead frames. In implementations the package does not include a spacer between the die and the first metallic layer and does not include a spacer between the die and the second metallic layer. In implementations the first insulator layer and the second insulator layer are exposed through the encapsulant or are mechanically coupled with metallic layers exposed through the encapsulant.
1. A method of forming a semiconductor package, comprising:
providing a first insulator layer coupled with a first metallic layer;
forming a recess in the first metallic layer;
mechanically coupling a semiconductor die at least partially within the recess, a perimeter of the semiconductor die located entirely within a perimeter of the recess;
mechanically coupling the semiconductor die with a second metallic layer, the second metallic layer coupled with a second insulator layer; and
at least partially encapsulating the first insulator layer, the first metallic layer, the semiconductor die, the second insulator layer, and the second metallic layer in an encapsulant to form a semiconductor package, wherein the first insulator layer and the second insulator layer are exposed through the encapsulant.
2. The method of claim 1 , wherein the semiconductor package does not comprise a spacer between the semiconductor die and the first metallic layer, and wherein the semiconductor package does not comprise a spacer between the semiconductor die and the second metallic layer.
3. The method of claim 1 , wherein a lead frame comprises the first metallic layer.
4. The method of claim 1 , wherein a lead frame comprises the second metallic layer.