IP Library Granted Patent US 10,779,409
Granted Patent B2
US 10,779,409 · App. 16/674,507 · Granted Sep 15, 2020

Printed circuit board

Inventors: Byung-Duk Na (Suwon-si, KR); Hye-Won Jung (Suwon-si, KR); Jae-Sung Sim (Suwon-si, KR); Mi-Sun Hwang (Suwon-si, KR); Hee-Joon Chun (Suwon-si, KR); Deok-Man Kang (Suwon-si, KR); Sun-A Kim (Suwon-si, KR)
Assignee: Samsung Electro-Mechanics Co., Ltd.
H05K1/116H05K1/0298H05K1/0366H05K1/05H05K3/4038
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Quick Facts
Patent No.
US 10,779,409
App. No.
16/674,507
Granted
Sep 15, 2020
Kind
B2
Abstract

A printed circuit board including: an insulating material; a metal layer stacked on a surface of the insulating material; and a via hole passing through the metal layer and the insulating material. The metal layer decreases in thickness in a region adjacent to the via hole, and an interface between the insulating material and the metal layer includes a region that is directed toward the via hole.

Claims (29)

1. A printed circuit board comprising:

an insulating material;

a metal layer stacked on a surface of the insulating material; and

a via hole passing through the metal layer and the insulating material, wherein

the metal layer decreases in thickness in a region adjacent to the via hole such that a boundary at which the insulating material contacts the metal layer is tapered toward the via hole to decrease the diameter of the via hole at the boundary.

2. The printed circuit board of claim 1 , wherein the metal layer has a smallest thickness in the region adjacent to the via hole.

3. The printed circuit board of claim 1 , wherein in a longitudinal section of the metal layer, a portion of the metal layer closest to the via hole is sharp.

4. The printed circuit board of claim 1 , wherein an inner side surface of the metal layer facing the via hole includes an outwardly convex curved surface.

5. The printed circuit board of claim 1 , wherein an interface between the insulating material and the metal layer is disposed at a lowest position of the interface closest to the via hole.

6. The printed circuit board of claim 1 , wherein an interface between the insulating material and the metal layer includes an outwardly convex curved surface that is directed toward the via hole.

7. The printed circuit board of claim 1 , wherein an inner side surface of the via hole passing through the insulating material includes a concave curved surface.

8. The printed circuit board of claim 1 , further comprising a conductor pattern disposed inside the insulating material and in contact with the via hole, wherein

the via hole passes through a surface of the conductor pattern.

9. The printed circuit board of claim 8 , wherein the surface of the conductor pattern includes a curved surface.

10. The printed circuit board of claim 9 , wherein the curved surface of the conductor pattern has a concave shape.

11. The printed circuit board of claim 8 , further comprising:

an electroless plating layer continuously disposed on a surface of the metal layer, an inner side surface of the via hole, and the surface of the conductor pattern; and

an electroplating layer disposed on the electroless plating layer.

12. The printed circuit board of claim 1 , wherein the insulating material includes a fiber reinforcing material, and

the fiber reinforcing material does not protrude inside of the via hole.

13. The printed circuit board of claim 1 , wherein the via hole comprises at least one surface substantially perpendicular to a planar direction of the insulating material.

14. The printed circuit board of claim 1 , further comprising a conductor pattern disposed inside the insulating material and in contact with the via hole, wherein

a surface of the conductor pattern through which the via hole passes comprises a flat surface.

15. A printed circuit board comprising:

an insulating material comprising a lower conductor pattern disposed therein;

a via connected to the lower conductor pattern through the insulating material; and

an upper conductor pattern disposed on an upper surface of the insulating material,

wherein the upper conductor pattern comprises: a ring-shaped metal layer disposed on the upper surface of the insulating material; an electroless plating layer disposed on an inner side surface and an upper surface of the metal layer; and an electroplating layer disposed on the electroless plating layer,

the metal layer decreases in thickness in a region adjacent to the via such that a boundary at which the insulating material contacts the metal layer is tapered toward the via to decrease the diameter of the via at the boundary.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 5, 2019
From: NA, BYUNG-DUK; JUNG, HYE-WON; SIM, JAE-SUNG; HWANG, MI-SUN; CHUN, HEE-JOON; KANG, DEOK-MAN; KIM, SUN-A
To: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Reel/Frame 050919/0798 →
Priority Claims (1)
KR 10-2018-0139076 · Nov 13, 2018 · national
Continuity (1)
Related Publication 20200154568A1 · May 14, 2020