Code and data sharing among multiple independent processors
A system includes a memory and multiple processors. The memory further includes a shared section and a non-shared section. The processors further include at least a first processor and a second processor, both of which read-only access to the shared section of the memory. The first processor and the second processor are operable to execute shared code stored in the shared section of the memory, and execute non-shared code stored in a first sub-section and a second sub-section of the non-shared section, respectively. The first processor and the second processor execute the share code according to a first scheduler and a second scheduler, respectively. The first scheduler operates independently of the second scheduler.
1. A system operative to share code, comprising:
a memory including a shared section and a non-shared section; and
a plurality of processors including at least a first processor and a second processor, the first processor and the second processor having read-only access to the shared section of the memory, wherein the first processor and the second processor are operable to:
execute shared code stored in the shared section of the memory according to a first scheduler and a second scheduler, respectively, wherein the first scheduler operates independently of the second scheduler,
execute non-shared code stored in a first sub-section and a second sub-section of the non-shared section, respectively, and
execute a read or write instruction having an operand at a first address in the first sub-section according to the shared code, and
wherein, to access the operand, the second processor at runtime is further operable to map the first address to a second address in the second sub-section according to an address mapping method.
2. The system of claim 1 , wherein the first processor and the second processor are further operable to write respective results of executing the shared code in the first sub-section and the second sub-section, respectively.
3. The system of claim 1 , further comprising a hardware circuit which at runtime re-directs a read or write operation performed by the second processor from a first address in the first sub-section to the second address in the second sub-section.
4. The system of claim 1 , wherein the first processor and the second processor are further operable to concurrently access the shared section of the memory.
5. The system of claim 1 , wherein the first processor and the second processor are operative to share read-only data stored in the shared section of the memory.
6. The system of claim 1 , wherein the first processor and the second processor execute the shared code independently of each other.
7. The system of claim 1 , wherein the first processor and the second processor have a same or compatible instruction set architecture (ISA).
8. The system of claim 1 , wherein the first processor and the second processor are operable to execute the shared code stored in the shared section without having a copy of the shared code in the non-shared section.
9. The system of claim 1 , wherein the memory and the plurality of processors are encased in a mobile device.
10. A method for code sharing, comprising
storing shared code in a shared section of a memory and non-shared code in a non-shared section of the memory, the non-shared section including a first sub-section and a second sub-section;
executing, by a first processor according to a first scheduler, the shared code in the shared section and the non-shared code in a first sub-section of the non-shared section;
executing, by a second processor according to a second scheduler, the shared code in the shared section and the non-shared code in a second sub-section of the non-shared section;
executing, by the first processor and the second processor, a read or write instruction having an operand at a first address in the first sub-section according to the shared code; and
mapping, by the second processor at runtime, the first address to a second address in the second sub-section to access the operand according to an address mapping method,
wherein the first processor and the second processor have read-only access to the shared section, and the second scheduler operates independently of the first scheduler.
11. The method of claim 10 , further comprising:
writing first results of executing the shared code in the first sub-section by the first processor; and
writing second results of executing the shared code in the second sub-section by the second processor.
12. The method of claim 10 , further comprising:
re-directing, by a hardware circuit, a read or write operation performed by the second processor from a first address in the first sub-section to the second address in the second sub-section.
13. The method of claim 10 , further comprising:
accessing, by the first processor and the second processor, the shared section of the memory concurrently.
14. The method of claim 10 , further comprising:
sharing, by the first processor and the second processor, read-only data stored in the shared section of the memory.
15. The method of claim 10 , wherein the first processor and the second processor execute the shared code independently of each other.
16. The method of claim 10 , wherein the first processor and the second processor have a same or compatible instruction set architecture (ISA).
17. The method of claim 10 , further comprising:
executing the shared code in the shared section without copying the shared code into the non-shared section.
18. The method of claim 10 , wherein the memory, the first processor and the second processor are encased in a mobile device.