High dynamic range receiver integrated into a chip package

1. A communications receiver, comprising:

a first bandpass filter configured to receive an input radio frequency (RF) signal and to generate a first filtered signal having a first frequency range with a first bandwidth greater than or equal to one octave above a lowest frequency in the first frequency range;

a balanced amplifier configured to receive the first filtered signal and suppress distortion products within the first bandwidth;

a first mixer configured to receive an output of the balanced amplifier and to mix the output with a first oscillator signal;

a second bandpass filter configured to receive an output from the first mixer and to generate a second filtered signal, wherein the second bandpass filter is centered at a first intermediate frequency that is higher than any frequency within the first bandwidth;

a second mixer configured to receive the second filtered signal and to mix the second filtered signal with a second oscillator signal; and

a third bandpass filter configured to receive an output from the second mixer and to generate a third filtered signal, wherein the third bandpass filter is centered at a second intermediate frequency that is lower than the first intermediate frequency.

2. The communications receiver of claim 1 , wherein the first bandwidth is at least 15 GHz.

3. The communications receiver of claim 1 , wherein the first oscillator signal is configured to be adjustable to within a second frequency range that is higher than the first intermediate frequency.

4. The communications receiver of claim 1 , wherein the first intermediate frequency is higher than at least 1.5 times a highest frequency within the first frequency range.

5. The communications receiver of claim 1 , wherein the second filtered signal has a second bandwidth that is less than or equal to half of the first bandwidth.

6. The communications receiver of claim 5 , wherein the third filtered signal has a third bandwidth that is substantially the same as the second bandwidth.

7. The communications receiver of claim 1 , wherein a frequency of the first oscillator signal is greater than the first intermediate frequency.

8. The communications receiver of claim 1 , wherein the first bandpass filter, the second bandpass filer, and the third bandpass filter are integrated into an interposer.

9. The communications receiver of claim 8 , wherein the balanced amplifier is provided on a first semiconductor chip that is coupled to a first location on the interposer, and the first mixer and the second mixer are each provided on a second semiconductor chip that is coupled to a second location on the interposer.

10. A system-in-package (SIP) device, comprising:

a three-dimensional interposer;

a first bandpass filter integrated into the three-dimensional interposer, wherein the first bandpass filter is configured to receive an input radio frequency (RF) signal and to generate a first filtered signal having a first frequency range with a first bandwidth;

a first integrated circuit chip on a first location of the three-dimensional interposer, wherein the first integrated circuit chip includes a balanced amplifier configured to receive the first filtered signal and suppress distortion products within the first frequency range;

a second integrated circuit chip on a second location of the three-dimensional interposer, wherein the second integrated circuit chip includes a first mixer and a second mixer, and wherein the first mixer is configured to receive an output of the balanced amplifier and to mix the output with a first oscillator signal;

a second bandpass filter integrated into the three-dimensional interposer, wherein the second bandpass filter is configured to receive an output from the first mixer and to generate a second filtered signal, wherein the second bandpass filter is centered at a first intermediate frequency that is higher than a highest frequency within the first frequency range, and wherein the second mixer is configured to receive the second filtered signal and to mix the second filtered signal with a second oscillator signal; and

a third bandpass filter integrated into the three-dimensional interposer, wherein the third bandpass filter is configured to receive an output from the second mixer and to generate a third filtered signal, and the third bandpass filter is centered at a second intermediate frequency that is lower than the first intermediate frequency.

11. The SIP device of claim 10 , wherein the first integrated circuit chip comprises gallium arsenide (GaAs), and the second integrated circuit chip comprises silicon germanium (SiGe).

12. The SIP device of claim 10 , further comprising a third integrated circuit chip on a third location of the three-dimensional interposer, the third integrated circuit chip comprising an analog-to-digital converter (ADC).

13. The SIP device of claim 10 , wherein the first bandwidth is greater than or equal to one octave above a lowest frequency in the first frequency range.

14. A communications receiver system, comprising:

an antenna configured to receive an RF signal;

an RF front-end circuitry configured to receive the RF signal from the antenna and to generate an amplified portion of the RF signal;

an analog-to-digital converter (ADC) configured to receive the amplified portion of the RF signal and to generate a digitized signal; and

a digital signal processor configured to receive the digitized signal;

wherein the RF front-end circuitry includes

a three-dimensional interposer;

a first bandpass filter integrated into the three-dimensional interposer, wherein the first bandpass filter is configured to receive the RF signal and to generate a first filtered signal having a first frequency range with a first bandwidth;

a first integrated circuit chip on a first location of the three-dimensional interposer, wherein the first integrated circuit chip includes a balanced amplifier configured to receive the first filtered signal and suppress distortion products within the first frequency range;

a second integrated circuit chip on a second location of the three-dimensional interposer, wherein the second integrated circuit chip includes a first mixer and a second mixer, wherein the first mixer is configured to receive an output of the balanced amplifier and to mix the output with a first oscillator signal;

a second bandpass filter integrated into the three-dimensional interposer, wherein the second bandpass filter is configured to receive an output from the first mixer and to generate a second filtered signal, wherein the second bandpass filter is centered at a first intermediate frequency that is higher than a highest frequency within the first frequency range, and wherein the second mixer is configured to receive the second filtered signal and to mix the second filtered signal with a second oscillator signal; and

a third bandpass filter integrated into the three-dimensional interposer, wherein the third bandpass filter is configured to receive an output from the second mixer and to generate a third filtered signal, and wherein the third bandpass filter is centered at a second intermediate frequency that is lower than the first intermediate frequency.

15. The communications receiver system of claim 14 , wherein the first bandwidth is greater than or equal to one octave above a lowest frequency in the first frequency range.

16. The communications receiver system of claim 14 , wherein the first integrated circuit chip comprises gallium arsenide (GaAs), and the second integrated circuit chip comprises silicon germanium (SiGe).

17. The communications receiver system of claim 14 , further comprising a third integrated circuit chip on a third location of the three-dimensional interposer, the third integrated circuit chip comprising the ADC.

18. The communications receiver system of claim 14 , wherein the three-dimensional interposer includes the antenna.