Memory system, memory controller and operating method of memory controller
A memory system includes a memory device including memory blocks and a memory controller configured to control the memory device. The memory device stores a firmware which includes binaries, and the binaries include a first binary and a second binary. The memory controller loads the firmware to a first region in a working memory, loads the first binary to a second region which is included in the first region, and loads the second binary to a third region which is included in the first region and is different from the second region. The memory controller stores information on an entry function corresponding to a target function included in the second binary, in a fourth region which is different from the first region. A start address of the second region is determined as a fixed value, and a start address of the third region is dynamically determined.
1. A memory system comprising:
a memory device including a plurality of memory blocks; and
a memory controller configured to control the memory device,
wherein the memory device stores firmware which includes a plurality of binaries including a first binary and a second binary,
wherein the memory controller loads the first binary to a second region which is included in a first region in a working memory, loads the second binary to a third region which is included in the first region and is different from the second region, and stores information on an entry function, corresponding to a target function in the second binary, in a fourth region which is different from the first region, and
wherein a start address of the second region is determined as a fixed value, and a start address of the third region is dynamically determined.
2. The memory system of claim 1 , wherein the memory controller loads the second binary to the third region at a time when the target function is called.
3. The memory system of claim 1 , wherein an offset between the fourth region and the first region is greater than or equal to a threshold offset.
4. The memory system of claim 3 , wherein the threshold offset is set depending on bits used in a memory addressing scheme of the memory controller.
5. The memory system of claim 1 , wherein an address of the target function is determined based on a compile time address of the target function, a compile time address of the second binary and a start address of the third region.
6. The memory system of claim 1 , wherein the memory controller includes a processor with a non-mapping based architecture for memory addresses.
7. The memory system of claim 1 , wherein the memory controller sets a logical memory address and a physical memory address to be the same.
8. The memory system of claim 1 , wherein the first binary includes at least one of a function for executing a read operation, a function for executing a program operation and a function for executing a map update operation.
9. The memory system of claim 1 , wherein the second binary includes at least one of a function for executing a booting operation and a function for executing a background operation.
10. The memory system of claim 9 , wherein the background operation includes at least one of a garbage collection (GC) operation, a wear leveling (WL) operation and a map flush operation.
11. A memory controller comprising:
a host interface configured to communicate with a host;
a memory interface configured to communicate with a memory device; and
a control circuit configured to control the memory device,
wherein the memory device stores firmware which includes a plurality of binaries including a first binary and a second binary,
wherein the control circuit loads the first binary to a second region which is included in a first region in a working memory, loads the second binary to a third region which is included in the first region and is different from the second region, and stores information on an entry function, corresponding to a target function in the second binary, in a fourth region which is different from the first region, and
wherein a start address of the second region is determined as a fixed value, and a start address of the third region is dynamically determined.
12. The memory controller of claim 11 , wherein the second binary is loaded to the third region at a time when the target function is called.
13. The memory controller of claim 11 , wherein an offset between the fourth region and the first region is greater than or equal to a threshold offset.
14. The memory controller of claim 11 , wherein an address of the target function is determined based on a compile time address of the target function, a compile time address of the second binary and a start address of the third region.
15. A method for operating a memory controller for controlling a memory device, comprising:
loading a first binary, among a plurality of binaries in firmware stored in the memory device, to a second region which is included in a first region in a working memory;
loading a second binary, among the plurality of binaries in the firmware, to a third region which is included in the first region and is different from the second region; and
storing information on an entry function, corresponding to a target function in the second binary, in a fourth region which is different from the first region,
wherein a start address of the second region is determined as a fixed value, and a start address of the third region is dynamically determined.
16. The method of claim 15 , wherein:
the second binary is loaded to the third region at a time when the target function is called.
17. The method of claim 15 , wherein an offset between the fourth region and the first region is greater than or equal to a threshold offset.
18. The method of claim 15 , wherein an address of the target function is determined based on a compile time address of the target function, a compile time address of the second binary and a start address of the third region.