IP Library Granted Patent US 11,221,926
Granted Patent B2
US 11,221,926 · App. 16/680,556 · Granted Jan 11, 2022

Information processing system and information processing apparatus

Inventors: Tatsuya Yamana (Kawasaki, JP); Reo Tajima (Nerima, JP)
Assignee: FUJITSU LIMITED
G06F11/2033G06F11/2028G06F11/2035G06F11/2046G06F11/2048G06F13/4022G06F2201/805
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Quick Facts
Patent No.
US 11,221,926
App. No.
16/680,556
Granted
Jan 11, 2022
Kind
B2
Abstract

An information processing system includes a plurality of information processing apparatuses each of which includes hardware, a control processor, and a switch circuit wherein when a failure of a first control processor in a first information processing apparatus of the plurality of information processing apparatuses is detected, a first switch circuit in the first information processing apparatus is configured to generate a connection of first hardware in the first information processing apparatus to a signal line between the first information processing apparatus and a second information processing apparatus of the plurality of information processing apparatuses, a second switch circuit in the second information processing apparatus is configured to generate a connection of a second control processor in the second information processing apparatus to the signal line, and the second control processor is configured to acquire information transmitted from the first hardware via the signal line.

Claims (108)

1. An information processing system comprising:

a plurality of information processing apparatuses each of which includes:

hardware,

a control processor coupled to the hardware, and

a switch circuit coupled to the hardware and the control processor;

wherein when a failure of a first control processor in a first information processing apparatus of the plurality of information processing apparatuses is detected:

a first switch circuit in the first information processing apparatus is configured to, in response to receiving a control signal, generate a connection of first hardware in the first information processing apparatus to a signal line between the first information processing apparatus and a second information processing apparatus of the plurality of information processing apparatuses,

a second switch circuit in the second information processing apparatus is configured to generate a connection of a second control processor in the second information processing apparatus to the signal line, and

the second control processor is configured to acquire information transmitted from the first hardware via the signal line; and

a management apparatus coupled to the plurality of information processing apparatuses, wherein:

the first control processor is configured to transmit information acquired from the first hardware to the management apparatus,

the management apparatus is configured to:

store the information received from the first control processor in a memory, and

in response to detecting the failure of the first control processor, transmit the stored information and identification information of the first information processing apparatus to the second control processor, and transmit the control signal to the first switch circuit, and

the second control processor is configured to cause the second switch circuit to generate the connection of the second control processor to the signal line in response to receiving the identification information of the first information processing apparatus.

2. The information processing system according to claim 1 , wherein

each switch circuit includes an input-side switch configured to switch a coupling between the hardware and another information processing apparatus of the plurality of information processing apparatuses, and an output-side switch configured to switch a coupling between the control processor and the other information processing apparatus,

the connection of the first hardware to the signal line is generated by a first input-side switch in the first switch circuit in accordance with the control signal, and

the connection of the second control processor to the signal line is generated by a second output-side switch in the second switch circuit in accordance with another control signal transmitted from the second control processor.

3. The information processing system according to claim 1 , wherein:

each of the plurality of information processing apparatuses further includes:

a control circuit configured to manage communication between a processor included in the hardware and the control processor, and

a communication switch circuit configured to switch a coupling among another information processing apparatus of the plurality of information processing apparatuses, the control circuit, and the control processor; and

wherein when the failure of the first control processor is detected:

a first communication switch circuit in the first information processing apparatus is configured to, in response to receiving a first communication control signal received from the management apparatus, generate a connection of a first control circuit in the first information processing apparatus to a communication signal line between the first information processing apparatus and the second information processing apparatus,

a second communication switch circuit in the second information processing apparatus is configured to, in response to receiving a second communication control signal from the management apparatus, generate a connection of the second control processor to the communication signal line, and

the second control processor is configured to communicate with a first processor included in the first hardware in the first information processing apparatus via the first control circuit coupled to the communication signal line.

4. The information processing system according to claim 3 , wherein

each communication switch circuit includes an input-side communication switch configured to switch a coupling between the control circuit and the other information processing apparatus, and an output-side communication switch configured to switch a coupling between the control processor and the other information processing apparatus,

the connection of the first control circuit to the communication signal line is generated by a first input-side communication switch in the first communication switch circuit in accordance with the first communication control signal, and

the connection of the second control processor to the communication signal line is generated by a second out-side communication switch circuit in the second communication switch circuit in accordance with the second communication control signal.

5. The information processing system according to claim 3 , wherein

the first control processor is configured to transmit setting information of communication between the first processor and the first control processor to the management apparatus,

the management apparatus is configured to:

store the setting information received from the first control processor, and

in response to detecting the failure of the first control processor, transmit the stored setting information to the second control processor, transmit the first communication control signal to the first communication switch circuit, and transmit the second communication control signal to the second communication switch circuit, and

the second control processor is configured to communicate with the first processor in accordance with the setting information received from the management apparatus.

6. An information processing system comprising:

a plurality of information processing apparatuses each of which includes:

hardware,

a control processor coupled to the hardware, and

a switch circuit coupled to the hardware and the control processor;

wherein when a failure of a first control processor in a first information processing apparatus of the plurality of information processing apparatuses is detected:

a first switch circuit in the first information processing apparatus is configured to, in response to receiving a control signal, generate a connection of first hardware in the first information processing apparatus to a signal line between the first information processing apparatus and a second information processing apparatus of the plurality of information processing apparatuses,

a second switch circuit in the second information processing apparatus is configured to generate a connection of a second control processor in the second information processing apparatus to the signal line,

the second control processor is configured to acquire information transmitted from the first hardware via the signal line,

the first control processor is configured to transmit information acquired from the first hardware to the second control processor, and

the second control processor is configured to, in response to detecting the failure of the first control processor, transmit the control signal to the first switch circuit, and cause the second switch circuit to generate the connection of the second control processor to the signal line;

each of the plurality of information processing apparatuses further includes:

a control circuit configured to manage communication between a processor included in the hardware and the control processor, and

a communication switch circuit configured to switch a coupling among another information processing apparatus of the plurality of information processing apparatuses, the control circuit, and the control processor; and

when the failure of the first control processor is detected:

a first communication switch circuit in the first information processing apparatus is configured to, in response to receiving a first communication control signal received from the second control processor, generate a connection of a first control circuit in the first information processing apparatus to a communication signal line between the first information processing apparatus and the second information processing apparatus,

a second communication switch circuit in the second information processing apparatus is configured to, in response to receiving a second communication control signal from the second control processor, generate a connection of the second control processor to the communication signal line, and

the second control processor is configured to communicate with a first processor included in the first hardware in the first information processing apparatus via the first control circuit coupled to the communication signal line.

7. The information processing system according to claim 6 , wherein

each communication switch circuit includes an input-side communication switch configured to switch a coupling between the control circuit and the other information processing apparatus, and an output-side communication switch configured to switch a coupling between the control processor and the other information processing apparatus,

the connection of the first control circuit to the communication signal line is generated by a first input-side communication switch in the first communication switch circuit in accordance with the first communication control signal, and

the connection of the second control processor to the communication signal line is generated by a second out-side communication switch circuit in the second communication switch circuit in accordance with the second communication control signal.

8. The information processing system according to claim 6 , wherein

the first control processor is configured to transmit setting information of communication between the first processor and the first control processor to the second control processor, and

the second control processor is configured to, in response to detecting the failure of the first control processor:

transmit the first communication control signal to the first communication switch circuit,

transmit the second communication control signal to the second communication switch circuit, and

communicate with the first processor in accordance with the setting information received from the first control processor.

9. An information processing system comprising:

a plurality of information processing apparatuses each of which includes:

hardware,

a control processor coupled to the hardware, and

a switch circuit coupled to the hardware and the control processor;

wherein when a failure of a first control processor in a first information processing apparatus of the plurality of information processing apparatuses is detected:

a first switch circuit in the first information processing apparatus is configured to, in response to receiving a control signal, generate a connection of first hardware in the first information processing apparatus to a signal line between the first information processing apparatus and a second information processing apparatus of the plurality of information processing apparatuses,

a second switch circuit in the second information processing apparatus is configured to generate a connection of a second control processor in the second information processing apparatus to the signal line, and

the second control processor is configured to acquire information transmitted from the first hardware via the signal line; and

a storage device coupled to the plurality of information processing apparatuses, wherein:

the first control processor is configured to transmit information acquired from the first hardware to the storage device, and

the second control processor is configured to, in response to detecting the failure of the first control processor:

acquire the information from the storage device,

transmit the control signal to the first switch circuit, and

cause the second switch circuit to generate the connection of the second control processor to the signal line in response to changing identification information of the second information processing apparatus.

10. The information processing system according to claim 9 , wherein:

each of the plurality of information processing apparatuses further includes:

a control circuit configured to manage communication between a processor included in the hardware and the control processor, and

a communication switch circuit configured to switch a coupling among another information processing apparatus of the plurality of information processing apparatuses, the control circuit, and the control processor; and

when the failure of the first control processor is detected,

a first communication switch circuit in the first information processing apparatus is configured to, in response to receiving a first communication control signal received from the second control processor, generate a connection of a first control circuit in the first information processing apparatus to a communication signal line between the first information processing apparatus and the second information processing apparatus,

a second communication switch circuit in the second information processing apparatus is configured to, in response to receiving a second communication control signal from the second control processor, generate a connection of the second control processor to the communication signal line, and

the second control processor is configured to communicate with a first processor included in the first hardware in the first information processing apparatus via the first control circuit coupled to the communication signal line.

11. The information processing system according to claim 10 , wherein

each communication switch circuit includes an input-side communication switch configured to switch a coupling between the control circuit and the other information processing apparatus, and an output-side communication switch configured to switch a coupling between the control processor and the other information processing apparatus,

the connection of the first control circuit to the communication signal line is generated by a first input-side communication switch in the first communication switch circuit in accordance with the first communication control signal, and

the connection of the second control processor to the communication signal line is generated by a second out-side communication switch circuit in the second communication switch circuit in accordance with the second communication control signal.

12. The information processing system according to claim 10 , wherein

the first control processor is configured to transmit setting information of communication between the first processor and the first control processor to the storage device, and

the second control processor is configured to, in response to detecting the failure of the first control processor:

acquire the setting information from the storage device,

transmit the first communication control signal to the first communication switch circuit,

transmit the second communication control signal to the second communication switch circuit, and

communicate with the first processor in accordance with the acquired setting information.

13. An information processing apparatus comprising:

hardware,

a control processor coupled to the hardware, and

a switch circuit coupled to the hardware and the control processor,

wherein when a failure of the control processor is detected:

the switch circuit is configured to, in response to receiving a control signal, generate a connection of the hardware to a signal line between the information processing apparatus and another information processing apparatus,

the hardware is configured to transmit information to another information processing apparatus via the signal line,

the control processor is configured to transmit information acquired from the hardware to a management apparatus which stores the information in a memory, and

the management apparatus transmits, in response to detecting the failure of the control processor, the stored information and identification information of the information processing apparatus to the another information processing apparatus, and the control signal to the switch circuit.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ORIGINAL COVER SHEET BY REMOVING PATENT NUMBER 10586039 PREVIOUSLY RECORDED ON REEL 69272 FRAME 546. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 1, 2025
From: FUJITSU LIMITED
To: FSAS TECHNOLOGIES INC.
Reel/Frame 070764/0091 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2024
From: FUJITSU LIMITED
To: FSAS TECHNOLOGIES INC.
Reel/Frame 069272/0546 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 12, 2019
From: YAMANA, TATSUYA; TAJIMA, REO
To: FUJITSU LIMITED
Reel/Frame 050993/0364 →
Priority Claims (1)
JP JP2018-218913 · Nov 22, 2018 · national
Continuity (1)
Related Publication 20200167249A1 · May 28, 2020