Storage device and operating method thereof

1. A memory controller for controlling one or more memory devices including a source stripe and a target stripe, the memory controller, comprising:

an operation controller configured to control the memory devices to perform read operations on first to third source pages and a source parity page in the source stripe and perform program operations on first to third target pages and a target parity page in the target stripe;

a program data determiner configured to determine first to third program data to be respectively programmed in the first to third target pages based on a success of each of the read operations on the first to third source pages, and to determine data read successfully from the first and second source pages as the first and second program data and determine recovery data as the third program data upon whether the read operation for the third source page has failed; and

a parity calculator configured to generate calculation data by using the first and second program data, and generate the recovery data by using source parity data stored in the source parity page and the calculation data.

2. The memory controller of claim 1 , wherein each of the first to third source pages and the source parity page are included in different memory devices, and

each of the first to third target pages and the target parity page are included in different memory devices.

3. The memory controller of claim 1 , wherein the parity calculator is configured to generate target parity data based on the calculation data and the recovery data.

4. The memory controller of claim 3 , wherein the operation controller is configured to control the one or more memory devices to store the recovery data in the third target page and to store the target parity data in the target parity page.

5. The memory controller of claim 1 , wherein the parity calculator is configured to generate the calculation data after the first and second program data are determined.

6. The memory controller of claim 1 , wherein the parity calculator is configured to generate the calculation data before the read operation for the third source page has failed.

7. The memory controller of claim 1 , wherein the parity calculator is configured to generate the recovery data upon receiving a determination that the read operation for the third source page has failed.

8. The memory controller of claim 1 , wherein the parity calculator is configured to generate the calculation data by performing an XOR calculation on the first and second program data.

9. The memory controller of claim 1 , further comprising an Error Correction Code (ECC) decoder configured to perform an error correction decoding to determine the success of each of the read operations on the first to third source pages.

10. A storage device, comprising:

one or more memory devices configured to perform read operations on first to third source pages and a source parity page, and perform program operations on first to third target pages and a target parity page; and

a memory controller in communication with the one or more memory devices and configured to:

determine whether the read operations on the first to third source pages have been successful,

determine data read from the first and second source pages whose read operation has been successfully performed as first and second program data, respectively,

generate calculation data by using the first and second program data,

generate recovery data based on source parity data read from the source parity page and the calculation data, and

determine the recovery data as third program data upon a determination that the read operation on the third source page is not successful,

wherein the first to third program data are to be respectively programmed in the first to third target pages.

11. The storage device of claim 10 , wherein the source parity page is configured to store the source parity data obtained by performing an XOR calculation on data stored in the first to third source pages, and

the target parity page is configured to store target parity data obtained by performing an XOR calculation on the first to third program data.

12. The storage device of claim 10 , wherein the first to third source pages and the source parity page are included in different memory devices, and

the first to third target pages and the target parity page are included in different memory devices.

13. The storage device of claim 10 , wherein the memory controller is configured to control the memory devices to store the recovery data in the third target page and the target parity data in the target parity page.

14. The storage device of claim 10 , wherein the memory controller is configured to generate the calculation data by performing XOR calculation on the first and second program data and generate the target parity data based on the calculation data and the recovery data.

15. The storage device of claim 10 , wherein the memory controller is configured to generate the calculation data before the read operation for the third source page has failed.

16. The storage device of claim 10 , wherein the memory controller is configured to generate the calculation data while the first and second program data are being programmed in the first and second target pages.

17. A method for operating a memory controller in communication with one or more memory devices, the method comprising:

providing read commands for reading first to third source pages and a source parity page in a source stripe to the one or more memory devices;

determining data read from the first and second source page on which read operations have been successful as first and second program data;

generating calculation data by using the first and second program data;

providing program commands for storing the first and second program data in first and second target pages in a target stripe to the one or more memory devices; and

generating recovery data by using source parity data read from the source parity page and the calculation data depending on whether a read operation on the third source page fails.

18. The method of claim 17 , wherein each page in the source stripe is included in difference memory devices, and

wherein each page in the target stripe is included in difference memory devices.

19. The method of claim 17 , further comprising:

providing program commands for storing the recovery data in a third target page of the target stripe to the one or more memory devices; and

providing program command for storing a target parity data generated based on the calculation data and the recovery data in a target parity page of the target stripe to the one or more memory devices.

20. The method of claim 17 , wherein the calculation data is generated by an XOR calculation on the first and second program data, and

wherein the recovery data is generated by an XOR calculation on the source parity data and the calculation data.