ADAPTIVE PENALTY TERM DETERMINATIONS IN APPLICATIONS OF QUANTUM COMPUTING TO ELECTRONIC DESIGN AUTOMATION PROCESSES
A system may include a quantum model engine configured to generate a quantum computing model to represent an electronic design automation (EDA) process for a circuit design. The EDA process may be a multi-patterning process to assign colors to geometric elements of the circuit design, and the quantum computing model may include an objective function that specifies a cost value for a given state of the quantum computing model. Generation of the quantum computing model may include adaptively determining a penalty term in the objective function based on a circuit analysis of the circuit design. The quantum model engine may also be configured to generate a color assignment for the geometric elements of the circuit design through the quantum computing model. The system may also include a manufacture support engine configured to use the color assignment to support manufacture of circuit layers of the circuit design through multiple manufacturing steps.
1 . A method comprising:
by a computing system:
generating a quantum computing model to represent an electronic design automation (EDA) process for a circuit design, wherein:
the EDA process comprises a multi-patterning process to assign colors to geometric elements of the circuit design;
the quantum computing model comprises an objective function that specifies a cost value for a given state of the quantum computing model, and wherein generating the quantum computing model comprises adaptively determining a penalty term in the objective function based on a circuit analysis of the circuit design; and
generating a color assignment for the geometric elements of the circuit design through the quantum computing model; and
using the color assignment to support manufacture of circuit layers of the circuit design through multiple manufacturing steps.
2 . The method of claim 1 , wherein adaptively determining a penalty term in the objective function based on a circuit analysis of the circuit design comprises:
identifying a given geometric element in the circuit design with a highest number of coloring constraints to other geometric elements in the circuit design; and
setting the penalty term in the objective function to be proportional to the highest number of coloring constraints for the given geometric element.
3 . The method of claim 1 , wherein adaptively determining a penalty term in the objective function based on a circuit analysis of the circuit design comprises:
relaxing at least some coloring constraints of the multi-patterning process;
computing an output for the relaxed multi-patterning process on the circuit design; and
setting the penalty term in the objective function to be proportional to a number of constraint violations in the computed output for the relaxed multi-patterning process on the circuit design.
4 . The method of claim 1 , wherein the EDA process comprises a triple-patterning process and wherein adaptively determining a penalty term in the objective function based on a circuit analysis of the circuit design comprises:
performing, as the circuit analysis, a double-patterning process on the circuit design;
determining a number of constraint violations in an output of the double-patterning process; and
setting the penalty term in the objective function to be proportional to the number of constraint violations in the output of the double-patterning process on the circuit design.
5 . The method of claim 1 , wherein the adaptively determined penalty term suppresses some, but not all, non-physical states from occurring in the quantum computing model, wherein the non-physical states correspond to outputs to the multi-patterning process that represent prohibited solutions of the multi-patterning process.
6 . The method of claim 5 , wherein the prohibited solutions of the multi-patterning process comprise outputs in which a geometric element is assigned more than one color, a geometric element is assigned no color, or combinations of both.
7 . The method of claim 1 , wherein generating the color assignment comprises determining a ground state with a minimum cost value for the quantum computing model through quantum annealing.
8 . A system comprising:
a quantum model engine configured to:
generate a quantum computing model to represent an electronic design automation (EDA) process for a circuit design, wherein:
the EDA process comprises a multi-patterning process to assign colors to geometric elements of the circuit design;
the quantum computing model comprises an objective function that specifies a cost value for a given state of the quantum computing model, and wherein generating the quantum computing model comprises adaptively determining a penalty term in the objective function based on a circuit analysis of the circuit design; and
generate a color assignment for the geometric elements of the circuit design through the quantum computing model; and
a manufacture support engine configured to use the color assignment to support manufacture of circuit layers of the circuit design through multiple manufacturing steps.
9 . The system of claim 8 , wherein the quantum model engine is configured to adaptively determine a penalty term in the objective function based on a circuit analysis of the circuit design by:
identifying a given geometric element in the circuit design with a highest number of coloring constraints to other geometric elements in the circuit design; and
setting the penalty term in the objective function to be proportional to the highest number of coloring constraints for the given geometric element.
10 . The system of claim 8 , wherein the quantum model engine is configured to adaptively determine a penalty term in the objective function based on a circuit analysis of the circuit design by:
relaxing at least some coloring constraints of the multi-patterning process;
computing an output for the relaxed multi-patterning process on the circuit design; and
setting the penalty term in the objective function to be proportional to a number of constraint violations in the computed output for the relaxed multi-patterning process on the circuit design.
11 . The system of claim 8 , wherein the EDA process comprises a triple-patterning process and wherein the quantum model engine is configured to adaptively determine a penalty term in the objective function based on a circuit analysis of the circuit design by:
performing, as the circuit analysis, a double-patterning process on the circuit design;
determining a number of constraint violations in an output of the double-patterning process; and
setting the penalty term in the objective function to be proportional to the number of constraint violations in the output of the double-patterning process on the circuit design.
12 . The system of claim 8 , wherein the adaptively determined penalty term suppresses some, but not all, non-physical states from occurring in the quantum computing model, wherein the non-physical states correspond to outputs to the multi-patterning process that represent prohibited solutions of the multi-patterning process.
13 . The system of claim 12 , wherein the prohibited solutions of the multi-patterning process comprise outputs in which a geometric element is assigned more than one color, a geometric element is assigned no color, or combinations of both.
14 . The system of claim 8 , wherein the quantum model engine is configured to generate the color assignment comprises determining a ground state with a minimum cost value for the quantum computing model through quantum annealing.
15 . A non-transitory machine-readable medium comprising instructions that, when executed by a processor, cause a computing system to:
generate a quantum computing model to represent an electronic design automation (EDA) process for a circuit design, wherein:
the EDA process comprises a multi-patterning process to assign colors to geometric elements of the circuit design;
the quantum computing model comprises an objective function that specifies a cost value for a given state of the quantum computing model, and wherein generating the quantum computing model comprises adaptively determining a penalty term in the objective function based on a circuit analysis of the circuit design; and
generate a color assignment for the geometric elements of the circuit design through the quantum computing model; and
use the color assignment to support manufacture of circuit layers of the circuit design through multiple manufacturing steps.
16 . The non-transitory machine-readable medium of claim 15 , wherein the instructions to adaptively determine a penalty term in the objective function based on a circuit analysis of the circuit design comprise instructions to:
identify a given geometric element in the circuit design with a highest number of coloring constraints to other geometric elements in the circuit design; and
set the penalty term in the objective function to be proportional to the highest number of coloring constraints for the given geometric element.
17 . The non-transitory machine-readable medium of claim 15 , wherein the instructions to adaptively determine a penalty term in the objective function based on a circuit analysis of the circuit design comprise instructions to:
relax at least some coloring constraints of the multi-patterning process;
compute an output for the relaxed multi-patterning process on the circuit design; and
set the penalty term in the objective function to be proportional to a number of constraint violations in the computed output for the relaxed multi-patterning process on the circuit design.
18 . The non-transitory machine-readable medium of claim 15 , wherein the EDA process comprises a triple-patterning process and wherein the instructions to adaptively determining a penalty term in the objective function based on a circuit analysis of the circuit design comprise instructions to:
perform, as the circuit analysis, a double-patterning process on the circuit design;
determine a number of constraint violations in an output of the double-patterning process; and
set the penalty term in the objective function to be proportional to the number of constraint violations in the output of the double-patterning process on the circuit design.
19 . The non-transitory machine-readable medium of claim 15 , wherein the adaptively determined penalty term suppresses some, but not all, non-physical states from occurring in the quantum computing model, wherein the non-physical states correspond to outputs to the multi-patterning process that represent prohibited solutions of the multi-patterning process; and
wherein the prohibited solutions of the multi-patterning process comprise outputs in which a geometric element is assigned more than one color, a geometric element is assigned no color, or combinations of both.
20 . The non-transitory machine-readable medium of claim 15 , wherein the instructions to generate the color assignment comprise instructions to determine a ground state with a minimum cost value for the quantum computing model through quantum annealing.