BACKSIDE ILLUMINATED GLOBAL SHUTTER IMAGE SENSOR WITH AN ANALOG MEMORY CHARGE COUPLED DEVICE
A global shutter image sensor may include a charge coupled device to store charge while mitigating dark current. The image sensor may include a first semiconductor substrate with a photodiode, a floating diffusion region, a transfer transistor coupled between the photodiode and the floating diffusion region, and a source follower transistor having a gate coupled to the floating diffusion region. The image sensor may include a second semiconductor substrate with an analog memory charge coupled device. The charge coupled device may include an input gate that is coupled to the source follower transistor in the first substrate, a charge injector, at least one storage gate, and an output gate. The charge coupled device may store samples correlated to charge on the floating diffusion region in the first substrate. During readout, the samples may sequentially be transferred to an additional floating diffusion region in the second substrate using the output gate.
1 . An image sensor comprising:
a photodiode;
a first floating diffusion region;
a transfer transistor that is configured to transfer charge from the photodiode to the first floating diffusion region;
a source follower transistor having a gate coupled to the first floating diffusion region;
an analog memory charge coupled device that includes an input gate that is coupled to the source follower transistor, at least one storage gate, and an output gate; and
a second floating diffusion region, wherein the output gate is configured to transfer charge from the analog memory charge coupled device to the second floating diffusion region.
2 . The image sensor defined in claim 1 , further comprising:
a row select transistor coupled between the source follower transistor and the input gate of the analog memory charge coupled device.
3 . The image sensor defined in claim 1 , wherein the analog memory charge coupled device comprises a charge injector.
4 . The image sensor defined in claim 3 , wherein the input gate is interposed between the charge injector and the at least one storage gate.
5 . The image sensor defined in claim 4 , wherein the at least one storage gate comprises first and second storage gates that are configured to store first and second respective samples associated with respective charge levels of the first floating diffusion region.
6 . The image sensor defined in claim 4 , wherein the at least one storage gate comprises first, second, third, and fourth storage gates that are configured to store first, second, third, and fourth respective samples associated with respective charge levels of the first floating diffusion region.
7 . The image sensor defined in claim 1 , wherein the source follower transistor is a first source follower transistor, wherein the gate is a first gate, and wherein the image sensor further comprises:
a second source follower transistor having a second gate that is coupled to the second floating diffusion region.
8 . The image sensor defined in claim 1 , further comprising:
a first reset transistor coupled to the first floating diffusion region; and
a second reset transistor coupled to the second floating diffusion region.
9 . The image sensor defined in claim 1 , further comprising:
a first semiconductor substrate, wherein the photodiode, first floating diffusion region, transfer transistor, and source follower transistor are formed in the first semiconductor substrate; and
a second semiconductor substrate, wherein the analog memory charge coupled device and the second floating diffusion region are formed in the second semiconductor substrate.
10 . The image sensor defined in claim 9 , further comprising:
a conductive interconnect layer that is coupled between the source follower transistor in the first semiconductor substrate and the input gate in the second semiconductor substrate.
11 . The image sensor defined in claim 1 , further comprising:
a first row select transistor coupled between the source follower transistor and the input gate of the analog memory charge coupled device;
an additional photodiode;
a third floating diffusion region;
an additional transfer transistor that is configured to transfer charge from the additional photodiode to the third floating diffusion region;
an additional source follower transistor having an additional gate coupled to the third floating diffusion region; and
a second row select transistor coupled between the additional source follower transistor and the input gate of the analog memory charge coupled device.
12 . The image sensor defined in claim 1 , wherein the input gate is a first input gate that is interposed between the first storage gate and a first charge injector and wherein the analog memory charge coupled device further comprises a second input gate that is interposed between the second storage gate and a second charge injector.
13 . The image sensor defined in claim 12 , further comprising:
an additional photodiode;
a third floating diffusion region;
an additional transfer transistor that is configured to transfer charge from the additional photodiode to the third floating diffusion region; and
an additional source follower transistor having an additional gate that is coupled to the third floating diffusion region, wherein the second input gate is coupled to the additional source follower transistor.
14 . An image sensor comprising:
a photodiode;
a first floating diffusion region that is coupled to the photodiode and that is configured to store charge;
a source follower transistor having a gate coupled to the first floating diffusion region;
a charge coupled device that is coupled to the source follower transistor and that is configured to store at least one charge sample that is correlated to the charge at the first floating diffusion region; and
a second floating diffusion region, wherein the charge coupled device is configured to transfer the at least one charge sample to the second floating diffusion region.
15 . The image sensor defined in claim 14 , further comprising:
a first semiconductor substrate, wherein the photodiode, the first floating diffusion region, and the source follower transistor are formed in the first semiconductor substrate; and
a second semiconductor substrate, wherein the charge coupled device and the second floating diffusion region are formed in the second semiconductor substrate.
16 . The image sensor defined in claim 15 , wherein the charge coupled device comprises a diffusion region configured to receive a charge injection voltage, at least first and second storage gates, a supplemental gate, an input gate interposed between the diffusion region and the supplemental gate, and an output gate interposed between the second storage gate and the second floating diffusion region.
17 . The image sensor defined in claim 16 , further comprising:
a conductive interconnect layer coupled between the first and second semiconductor substrates, wherein the conductive interconnect layer is electrically connected to the source follower transistor in the first semiconductor substrate and to the input gate in the second semiconductor substrate.
18 . An image sensor comprising:
a first semiconductor substrate;
a first photodiode formed in the first semiconductor substrate;
a first floating diffusion region formed in the first semiconductor substrate and coupled to the first photodiode;
a first source follower transistor in the first semiconductor substrate having a first gate coupled to the first floating diffusion region;
a second semiconductor substrate;
a second floating diffusion region in the second semiconductor substrate; and
a charge coupled device in the second semiconductor substrate that is coupled between the first source follower transistor and the second floating diffusion region.
19 . The image sensor defined in claim 18 , further comprising:
a second source follower transistor in the second semiconductor substrate having a second gate coupled to the second floating diffusion region.
20 . The image sensor defined in claim 19 , further comprising:
a first reset transistor in the first semiconductor substrate that is coupled to the first floating diffusion region;
a first row select transistor in the first semiconductor substrate that is coupled between the first source follower transistor and the charge coupled device;
a second reset transistor in the second semiconductor substrate that is coupled to the second floating diffusion region; and
a second row select transistor in the second semiconductor substrate that is coupled to the second source follower transistor.