IP Library Granted Patent US 11,138,084
Granted Patent B2
US 11,138,084 · App. 16/691,148 · Granted Oct 5, 2021

Negative path testing in a bootloader environment

Inventors: Daniel Muller (Palo Alto, CA); Andrei Warkentin (Cambridge, MA)
Assignee: VMware, Inc.
G06F11/26G06F9/4401G06F11/0793G06F11/2205G06F11/2215G06F11/2284G06F11/3065
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Quick Facts
Patent No.
US 11,138,084
App. No.
16/691,148
Granted
Oct 5, 2021
Kind
B2
Abstract

Negative path testing in a bootloader environment can include backing up a global state of a component under test, injecting a fault to trigger an error in the component under test in a bootloader environment, executing error handling instructions until a checkpoint of the component under test in the bootloader environment is reached, restoring the global state to the component under test from the backup, and restarting the component under test.

Claims (50)

1. A method for negative path testing in a bootloader environment, comprising:

backing up a global state of a component under test in a file, the file containing a mutable version of the global state and an immutable version of the global state;

injecting a fault to trigger an error in the component under test in a bootloader environment;

executing error handling instructions until a checkpoint of the component under test in the bootloader environment is reached;

restoring the global state to the component under test from the backup by using the immutable version of the global state; and

restarting the component under test.

2. The method of claim 1 , wherein restarting the component under test comprises restarting the component under test while in the bootloader environment.

3. The method of claim 1 , further comprising injecting a second fault to trigger a second error in the component under test after restarting the component under test.

4. The method of claim 1 , further comprising:

backing up the global state of the component under test;

injecting a different fault to trigger a different error in the component under test for each iteration;

executing error handling instructions until a checkpoint of the component under test;

restoring the global state to the component under test from a previous backup; and

restarting the component under test.

5. The method of claim 4 , further comprising:

maintaining a count of a quantity of iterations that is stored separately from the global state such that the count is not backed up or restored; and

iterating until the count equals a predefined quantity of modelled errors.

6. The method of claim 1 , further comprising:

injecting a different fault to trigger a different error in the component under test for each iteration without iteratively backing up the global state;

executing error handling instructions until a checkpoint of the component under test is reached;

restoring the global state to the component under test from the backup; and

restarting the component under test.

7. The method of claim 1 , further comprising:

modeling the error in the component under test; and

developing the error handling instructions based on the modelling.

8. A non-transitory computer readable medium storing instructions for negative path testing in a bootloader environment, the instructions, when executed by a processor, cause the processor to at least:

back up a global state of a component under test in a file, the file containing a mutable version of the global state and an immutable version of the global state;

inject a fault to trigger an error in the component under test in a bootloader environment;

execute error handling instructions until a checkpoint of the component under test in the bootloader environment is reached;

restore the global state to the component under test from the backup by using the immutable version of the global state; and

restart the component under test.

9. The non-transitory computer readable medium of claim 8 , wherein the instructions cause the processor to perform processing resource architecture-specific operations to ensure that the processing resource is in an expected state for the entry point to the component under test prior to branching to the entry point.

10. The non-transitory computer readable medium of claim 8 , wherein the instructions are executed in a bootloader environment.

11. The non-transitory computer readable medium of claim 8 , wherein the instructions cause the processor to maintain a state of a plurality of variables across reentrances to the entry point in a particular section separate from the data sections wherein the particular section is not subject to the instructions to save and to restore the global state.

12. The non-transitory computer readable medium of claim 11 , wherein a first variable of the plurality of variables comprises a counter for a quantity of reentries to the entry point.

13. The non-transitory computer readable medium of claim 12 , wherein a second variable of the plurality of variables comprises a value of a user-selectable option that defines whether the global state is to be saved each time the entry point is reentered after an initial reentry.

14. The non-transitory computer readable medium of claim 11 , wherein the instructions to inject the fault comprises instructions to inject a different fault to trigger a different error for each reentrance to the entry point.

15. A system for negative path testing in a bootloader environment, comprising:

at least one processor; and

a memory storing instructions executable by the processor, the instructions causing the at least one processor to at least:

back up a global state of a component under test in a file, the file containing a mutable version of the global state and an immutable version of the global state;

inject a fault to trigger an error in the component under test in a bootloader environment;

execute error handling instructions until a checkpoint of the component under test in the bootloader environment is reached;

restore the global state to the component under test from the backup by using the immutable version of the global state; and

restart the component under test.

16. The system of claim 15 , wherein the instructions cause the processor to perform processing resource architecture-specific operations to ensure that the processing resource is in an expected state for the entry point to the component under test prior to branching to the entry point.

17. The system of claim 15 , wherein the instructions are executed in a bootloader environment.

18. The system of claim 17 , wherein the instructions cause the at least one processor to maintain a state of a plurality of variables across reentrances to the entry point in a particular section separate from the data sections and wherein the particular section is not subject to the instructions to save and to restore the global state.

19. The system of claim 18 , wherein a second variable of the plurality of variables comprises a value of a user-selectable option that defines whether the global state is to be saved each time the entry point is reentered after an initial reentry.

20. The system of claim 18 , wherein the instructions to inject the fault comprises instructions to inject a different fault to trigger a different error for each reentrance to the entry point.

Assignments (1)
CHANGE OF NAME Recorded Apr 15, 2024
From: VMWARE, INC.
To: VMWARE LLC
Reel/Frame 067102/0314 →