Signaling For Multi-Reference Line Prediction And Multi-Hypothesis Prediction

1 . An electronic apparatus comprising:

a video decoder circuit configured to perform operations comprising:

receiving data for a block of pixels from a bitstream to be decoded as a current block of a current picture of a video;

parsing a first syntax element from the bitstream for a first coding mode in a particular set of two or more coding modes, wherein each of the particular set of coding modes modifies a merge candidate or an inter-prediction that is generated based on the merge candidate;

enabling the first coding mode and disabling one or more other coding modes in the particular set of coding modes, wherein the disabled one or more coding modes in the particular set of coding modes are disabled without parsing syntax elements for the disabled coding modes; and

decoding the current block by using the enabled first coding mode and bypassing the disabled coding modes.

2 . The electronic apparatus of claim 1 , wherein the particular set of coding modes comprises a coding mode that modifies the inter-prediction by adding an intra-prediction.

3 . The electronic apparatus of claim 2 , wherein the added intra prediction is generated by using only one reference tier that is a nearest reference tier for the current block.

4 . The electronic apparatus of claim 1 , wherein the particular set of coding modes comprise a coding mode that modifies the merge candidate by an offset and the modified merge candidate is used to generate the inter-prediction.

5 . The electronic apparatus of claim 1 , wherein the particular set of coding modes comprise a coding mode that modifies the generated inter-prediction by weighted sum with another inter-prediction that is generated based on another merge candidate.

6 . The electronic apparatus of claim 1 , wherein coding modes in the particular set of coding modes other than the first coding mode are inferred to be disabled based on the first syntax element.

7 . An electronic apparatus comprising:

a video encoder circuit configured to perform operations comprising:

receiving data for a block of pixels to be encoded as a current block of a current picture of a video;

signaling a first syntax element in a bitstream for a first coding mode in a particular set of two or more coding modes, wherein each coding mode of the particular set of coding modes modifies a merge candidate or an inter-prediction that is generated based on the merge candidate;

enabling the first coding mode and disabling one or more other coding modes in the particular set of coding modes, wherein the disabled one or more coding modes in the particular set of coding modes are disabled without signaling syntax elements for the disabled coding modes; and

encoding the current block in the bitstream by using the enabled first coding mode and bypassing the disabled coding modes.

8 . A video coding method comprising:

receiving data for a block of pixels to be decoded as a current block of a current picture of a video;

receiving a first syntax element for a first coding mode in a particular set of two or more coding modes, wherein each of the particular set of coding modes modifies a merge candidate or an inter-prediction that is generated based on the merge candidate;

enabling the first coding mode and disabling one or more other coding modes in the particular set of coding modes, wherein the disabled one or more coding modes in the particular set of coding modes are disabled without parsing syntax elements for the disabled coding modes; and

decoding the current block by using the enabled first coding mode and bypassing the disabled coding modes.