IP Library Granted Patent US 10,936,411
Granted Patent B2
US 10,936,411 · App. 16/692,200 · Granted Mar 2, 2021

Memory scrub system

Inventors: Ching-Lung Chao (Austin, TX); Shih-Hao Wang (New Taipei, TW); Zhengyu Yang (Fremont, CA)
Assignee: Dell Products L.P.
G06F11/106G06F9/4401G06F11/0772G06F13/24G11C29/52
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Quick Facts
Patent No.
US 10,936,411
App. No.
16/692,200
Granted
Mar 2, 2021
Kind
B2
Abstract

A memory scrubbing system includes a persistent memory device coupled to an operating system (OS) and a Basic Input/Output System (BIOS). During a boot process and prior to loading the OS, the BIOS retrieves a known memory location list that identifies known memory locations of uncorrectable errors in the persistent memory device and performs a partial memory scrubbing operation on the known memory locations. The BIOS adds any known memory locations that maintain an uncorrectable error to a memory scrub error list. The BIOS then initiates a full memory scrubbing operation on the persistent memory device, cause the OS to load and enter a runtime environment while the full memory scrubbing operation is being performed, and provides the memory scrub error list to the OS.

Claims (61)

1. A memory error management system, comprising:

a chassis;

a memory device located in the chassis; and

a memory scrubbing subsystem that is located in the chassis and that is coupled to the memory device, wherein the memory scrubbing subsystem is configured to:

identify, during a boot process, known memory locations of uncorrectable errors in the memory device;

determine, during the boot process and while performing a partial memory scrubbing operation on the known memory locations of uncorrectable errors, whether any of the known memory locations of uncorrectable errors maintain an uncorrectable error;

initiate a full memory scrubbing operation on the memory device;

enter a runtime environment while the full memory scrubbing operation is being performed; and

provide the known memory locations of uncorrectable errors that maintain an uncorrectable error to a memory location exclusion subsystem.

2. The system of claim 1 , wherein the memory location exclusion subsystem is configured to:

exclude the known memory locations of uncorrectable errors that maintain an uncorrectable error from use during the runtime environment.

3. The system of claim 1 , wherein the memory scrubbing subsystem is further configured to:

detect an uncorrectable error in a first memory location of the memory device during the full memory scrubbing operation that is being performed while in the runtime environment; and

provide an interrupt to the memory location exclusion subsystem in response to detecting the uncorrectable error in the first memory location of the memory device.

4. The system of claim 3 , wherein the memory location exclusion subsystem is configured to:

exclude, in response to receiving the interrupt, the first memory location that the memory scrubbing subsystem detected as having an uncorrectable error during the full memory scrubbing operation from use.

5. The system of claim 3 , wherein the memory scrubbing subsystem is further configured to:

add the first memory location to a known memory location list that identifies known memory locations of uncorrectable errors in the memory device.

6. The system of claim 1 , wherein the memory scrubbing subsystem is further configured to:

complete the full memory scrubbing operation that is being performed while in the runtime environment and, in response, provide an interrupt to the memory location exclusion subsystem indicating that the full memory scrubbing operation has completed, wherein the memory location exclusion subsystem is configured to obtain the known memory locations of uncorrectable errors that maintain an uncorrectable error in response to receiving the interrupt.

7. The system of claim 1 , wherein the memory scrubbing subsystem is further configured to:

receive a command from the memory location exclusion subsystem to begin the full memory scrubbing operation of the memory device while the full memory scrubbing operation that was initiated by the memory scrubbing subsystem is being performed; and

notify the memory location exclusion subsystem that the full memory scrubbing operation of the memory device is already in progress.

8. An Information Handling System (IHS), comprising:

a processing subsystem; and

a memory subsystem that is coupled to the processing subsystem and that includes instructions that, when executed by the processing subsystem, causes the processing subsystem to provide a memory scrubbing engine that is configured to:

identify, during a boot process, known memory locations of uncorrectable errors in a memory device;

determine, during the boot process and while performing a partial memory scrubbing operation on the known memory locations of uncorrectable errors, whether any of the known memory locations of uncorrectable errors maintain an uncorrectable error;

initiate a full memory scrubbing operation on the memory device;

enter a runtime environment while the full memory scrubbing operation is being performed; and

provide the known memory locations of uncorrectable errors that maintain an uncorrectable error to a memory location exclusion subsystem.

9. The IHS of claim 8 , wherein the providing the known memory locations of uncorrectable errors that maintain an uncorrectable error to the memory location exclusion subsystem causes the memory location exclusion subsystem to exclude the known memory locations of uncorrectable errors that maintain an uncorrectable error from use.

10. The IHS of claim 8 , wherein the memory scrubbing engine is further configured to:

detect an uncorrectable error in a first memory location of the memory device during the full memory scrubbing operation that is being performed while in the runtime environment; and

provide an interrupt to the memory location exclusion subsystem in response to detecting the uncorrectable error in the first memory location of the memory device.

11. The IHS of claim 10 , wherein the memory scrubbing engine is further configured to:

add the first memory location to a known memory location list that identifies known memory locations of uncorrectable errors in the memory device.

12. The IHS of claim 8 , wherein the memory scrubbing engine is further configured to:

complete the full memory scrubbing operation that is being performed while in the runtime environment and, in response, provide an interrupt to the memory location exclusion subsystem indicating that the full memory scrubbing operation has completed, wherein the interrupt is configured to cause the memory location exclusion subsystem to obtain the known memory locations of uncorrectable errors that maintain an uncorrectable error.

13. The IHS of claim 8 , wherein the memory scrubbing engine is further configured to:

receive a command from the memory location exclusion subsystem to begin the full memory scrubbing operation of the memory device while the full memory scrubbing operation that was initiated by the memory scrubbing engine is being performed; and

notify the memory location exclusion subsystem that the full memory scrubbing operation of the memory device is already in progress.

14. A method of memory scrubbing, comprising:

identifying, by a memory scrubbing subsystem during a boot process, known memory locations of uncorrectable errors in a memory device;

determining, by the memory scrubbing subsystem during the boot process and while performing a partial memory scrubbing operation on the known memory locations of uncorrectable errors, whether any of the known memory locations of uncorrectable errors maintain an uncorrectable error;

initiating, by the memory scrubbing subsystem, a full memory scrubbing operation on the memory device;

entering, by the memory scrubbing subsystem, a runtime environment while the full memory scrubbing operation is being performed; and

providing, by the memory scrubbing subsystem, the known memory locations of uncorrectable errors that maintain an uncorrectable error to a memory location exclusion subsystem.

15. The method of claim 14 , wherein the providing the known memory locations of uncorrectable errors that maintain an uncorrectable error to the memory location exclusion subsystem causes the memory location exclusion subsystem to exclude the known memory locations of uncorrectable errors that maintain an uncorrectable error from use.

16. The method of claim 14 , further comprising:

detecting, by the memory scrubbing subsystem, an uncorrectable error in a first memory location of the memory device during the full memory scrubbing operation that is being performed while in the runtime environment; and

providing, by the memory scrubbing subsystem, an interrupt to the memory location exclusion subsystem in response to detecting the uncorrectable error in the first memory location of the memory device.

17. The method of claim 16 , further comprising:

excluding, by the memory location exclusion subsystem in response to receiving the interrupt, the first memory location that the memory scrubbing subsystem detected as having an uncorrectable error during the full memory scrubbing operation from use.

18. The method of claim 16 , further comprising:

adding, by the memory scrubbing subsystem, the first memory location to a known memory location list that identifies known memory locations of uncorrectable errors in the memory device.

19. The method of claim 14 , further comprising:

completing, by the memory scrubbing subsystem, the full memory scrubbing operation that is being performed while in the runtime environment and, in response, providing an interrupt to the memory location exclusion subsystem indicating that the full memory scrubbing operation has completed, wherein the interrupt causes the memory location exclusion subsystem to obtain the known memory locations of uncorrectable errors that maintain an uncorrectable error.

20. The method of claim 14 , further comprising:

receiving, by the memory scrubbing subsystem, a command from the memory location exclusion subsystem to begin the full memory scrubbing operation of the memory device while the full memory scrubbing operation that was initiated by the memory scrubbing subsystem is being performed; and

notifying, by the memory scrubbing subsystem, the memory location exclusion subsystem that the full memory scrubbing operation of the memory device is already in progress.

Assignments (10)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053311/0169) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060438/0742 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052216/0758) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060438/0680 →
RELEASE OF SECURITY INTEREST AF REEL 052243 FRAME 0773 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058001/0152 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 053311/0169 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 26, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 052243/0773 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Mar 24, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052216/0758 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 22, 2019
From: YANG, ZHENGYU
To: DELL PRODUCTS L.P.
Reel/Frame 051090/0526 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 22, 2019
From: CHAO, CHING-LUNG; WANG, SHIH-HAO
To: DELL PRODUCTS L.P.
Reel/Frame 051091/0704 →