Iterating single instruction, multiple-data (SIMD) instructions

1. A system comprising:

a scheduler operative to schedule a single instruction, multiple data (SIMD) thread;

one or more processors operative to execute the SIMD thread; and

logic encoded in one or more non-transitory computer-readable storage media for execution by the one or more processors and when executed operative to cause the one or more processors to perform operations comprising:

initiating, by the scheduler, the SIMD thread;

fetching, by the one or more processors, a plurality of instructions for the SIMD thread from a memory;

determining, by a thread arbiter of the processor, at least one instruction of the plurality of instructions that is a walk instruction block, wherein the walk instruction block includes a walk-endwalk pair of instructions;

iterating a block of instructions within the walk-endwalk pair of instructions of the walk instruction block for a subset of channels of the SIMD thread, wherein the walk-endwalk instructions are responsible for iterating the block of instructions when a size of the SIMD thread is greater than a maximum native SIMD instruction width, and an execution mask is responsible for iterating the block of instructions when the size of the SIMD thread is less than the maximum native SIMD instruction width, wherein the walk instruction block includes a walk size, and wherein the walk size is a number of channels in the subset of channels of the SIMD thread that are processed in the iterating in association with the walk instruction block;

providing, by the thread arbiter, the walk instruction block to a code block iterator; and

executing, by the thread arbiter, the walk instruction block based on the walk size.

2. The system of claim 1 , wherein the SIMD thread includes a dispatch mask, and wherein the dispatch mask indicates which channels of a plurality of channels are enabled and/or indicates which channels of the plurality of channels are disabled at an initial point in time.

3. The system of claim 1 , wherein the walk instruction block involves processing data from the subset of the channels of the plurality of channels during execution of an iteration of a block of instructions for the SIMD thread.

4. The system of claim 1 , wherein the logic when executed is further operable to cause the one or more processors to perform operations comprising generating, by the code block iterator, a walk mask of the SIMD thread, wherein the walk mask indicates which subset of channels that are enabled and/or disabled during a particular walk iteration of executing the plurality of instructions for the SIMD thread.

5. The system of claim 1 , wherein the logic when executed is further operable to cause the one or more processors to perform operations comprising generating, by the code block iterator, a walk mask of the SIMD thread based at least on the walk size and the execution mask, wherein the execution mask is a mask that is applied when performing the plurality of instructions for the SIMD thread during a particular iteration of executing instructions for the SIMD thread.

6. The system of claim 1 , wherein the logic when executed is further operable to cause the one or more processors to perform operations comprising utilizing a subset of walk registers of a plurality of walk registers to execute the walk instruction block.

7. The system of claim 1 , wherein the logic when executed is further operable to cause the one or more processors to perform operations comprising:

initiating the walk instruction block during execution of a first iteration of executing instructions for the SIMD thread;

ending the walk instruction block;

initiating a second walk instruction block during execution of a second iteration of executing instructions for the SIMD thread; and

ending the second walk instruction block.

8. A non-transitory computer-readable storage medium with program instructions stored thereon, the program instructions when executed by one or more processors are operable to cause the one or more processors to perform operations comprising:

initiating, by a scheduler, a single instruction, multiple data (SIMD) thread, wherein the scheduler is operative to schedule the SIMD thread;

fetching, by the one or more processors, a plurality of instructions for the SIMD thread from a memory;

determining, by a thread arbiter of the processor, at least one instruction of the plurality of instructions that is a walk instruction block, wherein the walk instruction block includes a walk-endwalk pair of instructions:

iterating a block of instructions within the walk-endwalk pair of instructions of the walk instruction block for a subset of channels of the SIMD thread, wherein the walk-endwalk instructions are responsible for iterating the block of instructions when a size of the SIMD thread is greater than a maximum native SIMD instruction width, and an execution mask is responsible for iterating the block of instructions when the size of the SIMD thread is less than the maximum native SIMD instruction width, wherein the walk instruction block includes a walk size, and wherein the walk size is a number of channels in the subset of channels of the SIMD thread that are processed in the iterating in association with the walk instruction block;

providing, by the thread arbiter, the walk instruction block to a code block iterator; and

executing, by the thread arbiter, the walk instruction block based on the walk size.

9. The computer-readable storage medium of claim 8 , wherein the SIMD thread includes a dispatch mask, and wherein the dispatch mask indicates which channels of a plurality of channels are enabled and/or indicates which channels of the plurality of channels are disabled at an initial point in time.

10. The computer-readable storage medium of claim 8 , wherein the walk instruction block involves processing data from a subset of the channels of the plurality of channels during execution of an iteration of a block of instructions for the SIMD thread.

11. The computer-readable storage medium of claim 8 , wherein the instructions when executed are further operable to cause the one or more processors to perform operations comprising generating, by the code block iterator, a walk mask of the SIMD thread, wherein the walk mask indicates which subset of channels that are enabled and/or disabled during a particular walk iteration of executing the plurality of instructions for the SIMD thread.

12. The computer-readable storage medium of claim 8 , wherein the instructions when executed are further operable to cause the one or more processors to perform operations comprising generating, by the code block iterator, a walk mask of the SIMD thread based at least on the walk size and the execution mask, wherein the execution mask is a mask that is applied when performing the plurality of instructions for the SIMD thread during a particular iteration of executing instructions for the SIMD thread.

13. The computer-readable storage medium of claim 8 , wherein the instructions when executed are further operable to cause the one or more processors to perform operations comprising utilizing a subset of walk registers of a plurality of walk registers to execute the walk instruction block.

14. The computer-readable storage medium of claim 8 , wherein the instructions when executed are further operable to cause the one or more processors to perform operations comprising:

initiating the walk instruction block during execution of a first iteration of executing instructions for the SIMD thread;

ending the walk instruction block;

initiating a second walk instruction block during execution of a second iteration of executing instructions for the SIMD thread; and

ending the second walk instruction block.

15. A computer-implemented method comprising:

initiating, by a scheduler, a single instruction, multiple data (SIMD) thread, wherein the scheduler is operative to schedule the SIMD thread;

fetching, by the one or more processors, a plurality of instructions for the SIMD thread from a memory;

determining, by a thread arbiter of the processor, at least one instruction of the plurality of instructions that is a walk instruction block, wherein the walk instruction block includes a walk-endwalk pair of instructions;

iterating a block of instructions within the walk-endwalk pair of instructions of the walk instruction block for a subset of channels of the SIMD thread, wherein the walk-endwalk instructions are responsible for iterating the block of instructions when a size of the SIMD thread is greater than a maximum

native SIMD instruction width, and an execution mask is responsible for iterating the block of instructions when the size of the SIMD thread is less than the maximum native SIMD instruction width, wherein the walk instruction block includes a walk size, and wherein the walk size is a number of channels in the subset of channels of the SIMD thread that are processed in the iterating in association with the walk instruction block;

providing, by the thread arbiter, the walk instruction block to a code block iterator; and

executing, by the thread arbiter, the walk instruction block based on the walk size.

16. The method of claim 15 , wherein the SIMD thread includes a dispatch mask, and wherein the dispatch mask indicates which channels of a plurality of channels are enabled and/or indicates which channels of the plurality of channels are disabled at an initial point in time.

17. The method of claim 15 , wherein the walk instruction block involves processing data from a subset of the channels of the plurality of channels during execution of an iteration of a block of instructions for the SIMD thread.

18. The method of claim 15 , further comprising generating, by the code block iterator, a walk mask of the SIMD thread, wherein the walk mask indicates which subset of channels that are enabled and/or disabled during a particular walk iteration of executing the plurality of instructions for the SIMD thread.

19. The method of claim 15 , further comprising generating, by the code block iterator, a walk mask of the SIMD thread based at least on the walk size and the execution mask, wherein the execution mask is a mask that is applied when performing the plurality of instructions for the SIMD thread during a particular iteration of executing instructions for the SIMD thread.

20. The method of claim 15 , further comprising utilizing a subset of walk registers of a plurality of walk registers to execute the walk instruction block.