IP Library Granted Patent US 11,056,584
Granted Patent B2
US 11,056,584 · App. 16/693,598 · Granted Jul 6, 2021

Semiconductor device

Inventors: Kensuke Hata (Kariya, JP); Shinichi Hoshi (Kariya, JP); Hideo Matsuki (Kariya, JP); Youngshin Eum (Kariya, JP); Shigeki Takahashi (Kariya, JP)
Assignee: DENSO CORPORATION
H01L29/7787H01L29/41758H01L29/4236H01L29/802
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Quick Facts
Patent No.
US 11,056,584
App. No.
16/693,598
Granted
Jul 6, 2021
Kind
B2
Abstract

In a semiconductor device having an active region and an inactive region, the active region includes a channel forming layer with a heterojunction structure having first and second semiconductor layers, a gate structure portion having a MOS gate electrode, a source electrode and a drain electrode disposed on the second semiconductor layer with the gate structure portion interposed therebetween, a third semiconductor layer disposed at a position away from the drain electrode between the gate structure portion and the drain electrode and not doped with an impurity, a p-type fourth semiconductor layer disposed on the third semiconductor layer, and a junction gate electrode brought into contact with the fourth semiconductor layer. The junction gate electrode is electrically connected to the source electrode to have a same potential as a potential of the source electrode, and is disposed only in the active region.

Claims (25)

1. A semiconductor device having an active region and an inactive region that surrounds the active region, and comprising:

a lateral switching device disposed in the active region and including

a channel forming layer that is disposed on a substrate, includes a heterojunction structure having a first semiconductor layer made of a first GaN-based semiconductor forming a drift region and a second semiconductor layer made of a second GaN-based semiconductor having a band gap energy higher than a band gap energy of the first GaN-based semiconductor, and has a recessed portion provided in the second semiconductor layer,

a gate structure portion that includes a gate insulating film disposed in the recessed portion and a MOS gate electrode disposed on the gate insulating film and serving as a gate electrode of a MOS structure,

a source electrode and a drain electrode which are disposed on the second semiconductor layer in such a manner that the gate structure portion is interposed between the source electrode and the drain electrode,

a third semiconductor layer that is disposed on the second semiconductor layer at a position away from the drain electrode between the gate structure portion and the drain electrode, and is made of a third GaN-based semiconductor not doped with an impurity,

a fourth semiconductor layer that is disposed on the third semiconductor layer and is made of a fourth GaN-based semiconductor having a p-type, and

a junction gate electrode that is brought into contact with the fourth semiconductor layer;

a gate pad disposed in the inactive region and connected to the MOS gate electrode through a gate wire;

a source pad disposed in the inactive region and connected to the source electrode through a source wire; and

a drain pad disposed in the inactive region and connected to the drain electrode through a drain wire, wherein

the junction gate electrode is electrically connected to the source electrode to have a same potential as a potential of the source electrode, and is disposed only in the active region.

2. The semiconductor device according to claim 1 , wherein

the junction gate electrode has an annular shape surrounding the drain electrode.

3. The semiconductor device according to claim 1 , wherein

the drain electrode is connected to the drain pad disposed in the inactive region through the drain wire extending from the active region to the inactive region, and

the junction gate electrode is disposed at a position different from a position of the drain wire and surrounding the drain electrode.

4. The semiconductor device according to claim 1 , wherein

the source electrode is connected to the source pad disposed in the inactive region through the source wire extending from the active region to the inactive region,

the drain electrode is connected to the drain pad disposed in the inactive region through the drain wire extending from the active region to the inactive region, and

when the source electrode, the source pad, and the source wire are collectively referred to as source portions, and the drain electrode, the drain pad, and the drain wire are collectively referred to as drain portions, the junction gate electrode is disposed between all the source portions and all the drain portions.

5. The semiconductor device according to claim 1 , further comprising:

an interlayer insulating film covering the MOS gate electrode; and

an electrode layer disposed on the interlayer insulating film, wherein

the junction gate electrode is integrally connected with the source electrode through the electrode layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 25, 2019
From: HATA, KENSUKE; HOSHI, SHINICHI; MATSUKI, HIDEO; EUM, YOUNGSHIN; TAKAHASHI, SHIGEKI
To: DENSO CORPORATION
Reel/Frame 051101/0581 →
Priority Claims (1)
JP JP2017-124349 · Jun 26, 2017 · national
Continuity (2)
Continuation PCTJP2018020230 · May 25, 2018
Related Publication 20200091332A1 · Mar 19, 2020
Cited By (1)
US 12,278,272