IP Library Granted Patent US 11,114,989
Granted Patent B2
US 11,114,989 · App. 16/694,025 · Granted Sep 7, 2021

Power amplifying circuit

Inventors: Satoshi Goto (Kyoto, JP); Hideyuki Satou (Kyoto, JP); Satoshi Tanaka (Kyoto, JP)
Assignee: MURATA MANUFACTURING CO., LTD.
H03F3/245H03F1/0211H03F2200/102H03F2200/378H03F2200/451
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Quick Facts
Patent No.
US 11,114,989
App. No.
16/694,025
Granted
Sep 7, 2021
Kind
B2
Abstract

A power amplifying circuit includes an amplifier that amplifies a radio-frequency signal and a bypass capacitor section connected to a power supply terminal for supplying a power supply voltage to the amplifier. The bypass capacitor section includes a first capacitor, a second capacitor, and a first switch circuit. The first capacitor includes a first end connected to a power supply path, and a second end. The second capacitor includes a first end connected to the second end of the first capacitor and a second end connected to ground. The first switch circuit includes a first terminal connected to the second end of the first capacitor and the first end of the second capacitor, and a second terminal connected to the ground. The first switch circuit switches between connection and non-connection between the second end of the first capacitor and the ground.

Claims (33)

1. A power amplifying circuit comprising:

a transistor configured to amplify a radio-frequency signal; and

a bypass capacitor section connected to a path that connects a collector end or a drain end of the transistor to a power supply terminal, wherein:

the bypass capacitor section comprises a first capacitor, a second capacitor, and a first switch circuit,

a first end of the first capacitor is connected to the power supply terminal, and a second end of the first capacitor is connected to a first end of the second capacitor and a first terminal of the first switch circuit,

a second end of the second capacitor is connected to ground,

a second terminal of the first switch circuit is connected to ground, and

the first switching circuit is configured to selectively cause connection of the second end of the first capacitor to ground.

2. A power amplifying circuit comprising:

a transistor configured to amplify a radio-frequency signal; and

a bypass capacitor section connected to a path that connects a collector end or a drain end of the transistor to a power supply terminal, wherein:

the bypass capacitor section comprises a first capacitor, a second capacitor, and a first switch circuit,

a first end of the first capacitor is connected to the power supply terminal, and a second end of the first capacitor is connected to a first terminal of the first switch circuit and to a first terminal of the second capacitor,

a second terminal of the first switch circuit is connected to ground, and a third terminal of the first switch circuit is connected to a second end of the second capacitor, and

the first switch circuit is configured to selectively cause connection of the second capacitor to ground.

3. The power amplifying circuit according to claim 1 , wherein the transistor is a bipolar transistor.

4. The power amplifying circuit according to claim 2 , wherein the transistor is a bipolar transistor.

5. The power amplifying circuit according to claim 1 , wherein the transistor is a field-effect transistor.

6. The power amplifying circuit according to claim 2 , wherein the transistor is a field-effect transistor.

7. The power amplifying circuit according to claim 1 , wherein the first capacitor has a larger capacitance value than the second capacitor.

8. The power amplifying circuit according to claim 2 , wherein the first capacitor has a larger capacitance value than the second capacitor.

9. The power amplifying circuit according to claim 1 , wherein the first switch circuit is configured to selectively cause the second end of the first capacitor to be disconnected from ground when the power amplifying circuit operates in an envelope tracking control mode, and to selectively cause the second end of the first capacitor to be connected to ground when the power amplifying circuit operates in an average power tracking control mode.

10. The power amplifying circuit according to claim 2 , wherein the first switch circuit is configured to selectively cause the second end of the first capacitor to be disconnected from ground when the power amplifying circuit operates in an envelope tracking control mode, and to selectively cause the second end of the first capacitor to be connected to ground when the power amplifying circuit operates in an average power tracking control mode.

11. The power amplifying circuit according to claim 1 , wherein the second end of the second capacitor is directly connected to ground.

12. The power amplifying circuit according to claim 1 , wherein the bypass capacitor section further comprises:

a third capacitor having a first end connected to the second end of the second capacitor and a second end connected to ground, and

a second switch circuit configured to selectively connect the second end of the second capacitor to ground.

13. The power amplifying circuit according to claim 1 , wherein the bypass capacitor section further comprises a fourth capacitor having a first end connected to the power supply terminal and a second end connected to ground.

14. The power amplifying circuit according to claim 2 , wherein the bypass capacitor section further comprises a fourth capacitor having a first end connected to the power supply terminal and a second end connected to ground.

15. The power amplifying circuit according to claim 13 , wherein the bypass capacitor section further comprises a third switch circuit configured to selectively cause connection of the second end of the fourth capacitor to ground.

16. The power amplifying circuit according to claim 14 , wherein the bypass capacitor section further comprises a third switch circuit configured to selectively cause connection of the second end of the fourth capacitor to ground.

17. The power amplifying circuit according to claim 1 , wherein the first switch circuit comprises a field-effect transistor.

18. The power amplifying circuit according to claim 2 , wherein the first switch circuit comprises a field-effect transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 25, 2019
From: GOTO, SATOSHI; SATOU, HIDEYUKI; TANAKA, SATOSHI
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 051105/0525 →
Priority Claims (3)
JP JP2018-222238 · Nov 28, 2018 · national
JP JP2019-014642 · Jan 30, 2019 · national
JP JP2019-164813 · Sep 10, 2019 · national
Continuity (1)
Related Publication 20200169232A1 · May 28, 2020
Cited By (1)
US 12,249,997