Thin film transistor substrate and display panel

1. A thin film transistor substrate including a pixel region constructed with a plurality of pixels and a frame region surrounding the pixel region, the thin film transistor substrate comprising:

thin film transistors and pixel electrodes provided in each of the plurality of pixels respectively;

a plurality of gate signal lines extending in a first direction in the pixel region and supplying a gate signal to the thin film transistors in the plurality of pixels;

a plurality of gate lead-out lines and a plurality of dummy gate lead-out lines extending in a second direction different from the first direction in the pixel region;

a plurality of common lines extending in at least one of the first direction and the second direction in the pixel region, a common potential being applied to the plurality of common lines;

a common electrode provided opposite to the pixel electrode and electrically connected to the plurality of common lines;

a shield electrode formed in the frame region, the common potential being applied to the shield electrode; and

a plurality of first connection wirings respectively connecting the plurality of dummy gate lead-out lines and the shield electrode through respective first contact holes made in the frame region, wherein

the plurality of gate lead-out lines are connected to the plurality of gate signal lines at least at one point of a plurality of intersections between the plurality of gate signal lines and the plurality of gate lead-out lines, and

the common potential is applied to the plurality of dummy gate lead-out lines.

2. The thin film transistor substrate according to claim 1 , further comprising:

a plurality of source signal lines extending in the second direction in the pixel region and supplying a data signal to the thin film transistors in the plurality of pixels;

a gate terminal including a plurality of gate terminal electrodes connected to the plurality of gate lead-out lines respectively; and

a source terminal including a plurality of source terminal electrodes connected to the plurality of source signal lines respectively,

wherein the gate terminal and the source terminal are provided in one of a pair of long sides in the frame region of the thin film transistor substrate.

3. The thin film transistor substrate according to claim 1 , wherein the plurality of first connection wirings are formed in a layer identical to the pixel electrodes.

4. The thin film transistor substrate according to claim 1 , wherein the plurality of first connection wirings are formed in a layer identical to the common electrode.

5. The thin film transistor substrate according to claim 1 , wherein the plurality of first connection wirings are formed in a layer identical to a source-drain electrode of the thin film transistor.

6. The thin film transistor substrate according to claim 1 , wherein the shield electrode is formed in a layer identical to the plurality of dummy gate lead-out lines.

7. The thin film transistor substrate according to claim 1 , wherein the shield electrode is formed in a mesh shape.

8. The thin film transistor substrate according to claim 1 , wherein for the one first connection wiring, the first contact hole is made in at least two points of the dummy gate lead-out lines and on the shield electrode.

9. The thin film transistor substrate according to claim 1 , wherein the first contact hole is made in the other of the pair of long sides.

10. A display panel comprising:

the thin film transistor substrate according to claim 1 ; and

a counter substrate opposed to the thin film transistor substrate.