System on a chip (SoC) communications to prevent direct memory access (DMA) attacks
This disclosure describes system on a chip (SOC) communications that prevent direct memory access (DMA) attacks. An example SoC includes an encryption engine and a security processor. The encryption engine is configured to encrypt raw input data using a cipher key to form an encrypted payload. The security processor is configured to select the cipher key from a key store holding a plurality of cipher keys based on a channel ID describing a {source subsystem, destination subsystem} tuple for the encrypted payload, to form an encryption header that includes the channel ID, to encapsulate the encrypted payload with the encryption header that includes the channel ID to form a crypto packet, and to transmit the crypto packet to a destination SoC that is external to the SoC.
1. A system on a chip (SoC) comprising:
an encryption engine configured to encrypt raw input data using a cipher key to form an encrypted payload; and
a security processor configured to
select the cipher key from a key store holding a plurality of cipher keys based on a channel ID describing a {source subsystem, destination subsystem} tuple for the encrypted payload;
form an encryption header that includes the channel ID;
encapsulate the encrypted payload with the encryption header that includes the channel ID to form a crypto packet; and
transmit the crypto packet to a destination SoC that is external to the SoC.
2. The SoC of claim 1 , wherein to select the cipher key based on the channel ID, the security processor is configured to select the cipher key on a unique per-channel ID basis.
3. The SoC of claim 1 , wherein the security processor is configured to identify the channel ID at least in part by identifying, from a plurality of subsystems of the SoC, the source subsystem that originated the raw input data.
4. The SoC of claim 3 , further comprising a direct memory access (DMA) engine configured to load the raw input data from an address memory reserved for the source subsystem in a shared memory (SMEM) to a wireless memory (WMEM) of the SoC.
5. The SoC of claim 1 , wherein the SoC is coupled to an egress interface, and wherein to transmit the crypto packet to the destination SoC, the security processor is further configured to transmit the crypto packet to the destination SoC via the egress interface.
6. The SoC of claim 1 , wherein the SoC comprises a source SoC, and wherein to form the encryption header, the security processor is further configured to include a source SoC-identifier in the encryption header.
7. The SoC of claim 6 , wherein the security processor is further configured to:
apply the cipher key to the source SoC-identifier and the channel ID to form a cryptographic signature; and
sign the encryption header and encrypted payload of the crypto packet using the cryptographic signature.
8. The SoC of claim 1 , wherein the SoC is integrated into one of a head-mounted device (HMD) of an artificial reality system or a peripheral device of the artificial reality system.
9. A system on a chip (SoC) comprising:
a security processor configured to
receive, via an ingress interface, a crypto packet;
decapsulate the crypto packet to obtain an encryption header and an encrypted payload;
parse the encryption header to obtain a channel ID describing a {source subsystem, destination subsystem} tuple for the encrypted payload; and
select a decryption key from a key store holding a plurality of decryption keys based on the channel ID obtained from the encryption header; and
a decryption engine configured to decrypt the encrypted payload using the decryption key to form a decrypted payload.
10. The SoC of claim 9 , wherein to select the decryption key based on the channel ID, the security processor is configured select the decryption key on a unique per-channel ID basis.
11. The SoC of claim 9 , further comprising a direct memory access (DMA) engine configured to load the decrypted payload from a wireless memory (WMEM) of the SoC to an address memory reserved for the destination subsystem in a shared memory (SMEM).
12. The SoC of claim 9 , wherein the SoC comprises a destination SoC, and wherein the security processor is further configured to obtain, from the encryption header, a source SoC-identifier that identifies a source SoC external to the destination SoC.
13. The SoC of claim 12 , wherein the security processor is further configured to verify the received crypto packet based on a combination of the source SoC-identifier obtained from the encryption header, the channel ID obtained from the encryption header, and a cryptographic signature with which the encryption header and encrypted payload of the crypto packet are signed.
14. The SoC of claim 9 , wherein the SoC is integrated into one of a head-mounted device (HMD) of an artificial reality system or a peripheral device of the artificial reality system.
15. An artificial reality system comprising:
a head-mounted device (HMD) having an HMD system on a chip (SoC) comprising:
an encryption engine configured to encrypt raw input data using a cipher key to form an encrypted payload; and
a first security processor configured to:
select the cipher key from a key store holding a plurality of cipher keys based on a channel ID describing a {source subsystem, destination subsystem} tuple for the encrypted payload;
form an encryption header that includes the channel ID;
encapsulate the encrypted payload with the encryption header that includes the channel ID to form a crypto packet; and
transmit, via an egress interface, the crypto packet to a destination SoC.
16. The artificial reality system of claim 15 , further comprising:
a peripheral device communicatively coupled to the HMD, the peripheral device having a peripheral SoC, wherein the peripheral SoC is the destination SoC, and wherein the peripheral SoC comprises:
a second security processor configured to:
receive, via an ingress interface, the crypto packet;
decapsulate the crypto packet to obtain the encryption header and the encrypted payload;
parse the encryption header to obtain the channel ID describing the {source subsystem, destination subsystem} tuple for the encrypted payload; and
select a decryption key from a key store holding a plurality of decryption keys based on the channel ID obtained from the encryption header; and
a decryption engine configured to decrypt the encrypted payload using the decryption key to form a decrypted payload.
17. The artificial reality system of claim 16 , wherein to select the cipher key based on the channel ID, the first security processor is configured to select the cipher key on a unique per-channel ID basis, and wherein to select the decryption key based on the channel ID, the second security processor is configured select the decryption key on the unique per-channel ID basis.
18. The artificial reality system of claim 16 , wherein the HMD SoC comprises a source SoC, wherein to form the encryption header, the first security processor is further configured to include a source SoC-identifier in the encryption header, and wherein the first security processor is further configured to:
apply the cipher key to the source SoC-identifier and the channel ID to form a cryptographic signature; and
sign the encryption header and encrypted payload of the crypto packet using the cryptographic signature.
19. The artificial reality system of claim 18 , wherein the peripheral SoC comprises a destination SoC, wherein the second security processor is further configured to obtain, from the encryption header, the source SoC-identifier that identifies the HMD SoC as the source SoC, and wherein the second security processor is further configured to verify the received crypto packet based on a combination of the source SoC-identifier obtained from the encryption header, the channel ID obtained from the encryption header, and the cryptographic signature with which the encryption header and encrypted payload of the crypto packet are signed.
20. The artificial reality system of claim 16 ,
wherein the HMD SoC further comprises a first direct memory access (DMA) engine configured to load the raw input data from address memory reserved for the source subsystem in a first shared memory (SMEM) to a first wireless memory (WMEM) of the HMD SoC, and
wherein the peripheral SoC further comprises a second DMA engine configured to load the decrypted payload from a second wireless memory WMEM of the peripheral SoC to address memory reserved for the destination subsystem in a second SMEM of the peripheral device.
21. An artificial reality system comprising:
a peripheral device having a peripheral system on a chip (SoC) comprising:
an encryption engine configured to encrypt raw input data using a cipher key to form an encrypted payload; and
a first security processor configured to:
select the cipher key from a key store holding a plurality of cipher keys based on a channel ID describing a {source subsystem, destination subsystem} tuple for the encrypted payload;
form an encryption header that includes the channel ID;
encapsulate the encrypted payload with the encryption header that includes the channel ID to form a crypto packet; and
transmit, via an egress interface, the crypto packet to a destination SoC.
22. The artificial reality system of claim 21 , further comprising:
a head-mounted device (HMD) communicatively coupled to the peripheral device, the HMD having an HMD SoC, wherein the HMD SoC is the destination SoC, and wherein the HMD SoC comprises:
a second security processor configured to:
receive, via an ingress interface, the crypto packet;
decapsulate the crypto packet to obtain the encryption header and the encrypted payload;
parse the encryption header to obtain the channel ID describing the {source subsystem, destination subsystem} tuple for the encrypted payload; and
select a decryption key from a key store holding a plurality of decryption keys based on the channel ID obtained from the encryption header; and
a decryption engine configured to decrypt the encrypted payload using the decryption key to form a decrypted payload.