Interposers for microelectronic devices
Described are semiconductor interposer, and microelectronic device assemblies incorporating such semiconductor interposers. The described interposers include multiple redistribution structures on each side of the core; each of which may include multiple individual redistribution layers. The interposers may optionally include circuit elements, such as passive and/or active circuit. The circuit elements may be formed at least partially within the semiconductor core.
1. An interposer, comprising:
mounting sites on a first surface of the interposer for multiple semiconductor device structures;
contact structures on a second surface of the interposer forming electrical connections to other structures;
a core comprising a non-organic material comprising a semiconductor material;
multiple vertical contacts extending through the core;
a first set of multiple redistribution layers formed one over a first side of the core;
a second set of multiple redistribution layers formed over a second side of the core opposite the first side; and
one or more circuit components formed at least partially in the semiconductor material of the core.
2. The interposer of claim 1 , further comprising multiple mounting sites on a first surface of the interposer for mounting multiple semiconductor device structures to the interposer.
3. The interposer of claim 2 , wherein the multiple mounting sites each include one or more arrays of contacts forming a memory device interface.
4. The interposer of claim 3 , wherein the memory device interface is configured to couple with a memory device comprising multiple vertically stacked memory die.
5. The interposer of claim 4 , wherein the memory device interface defines a high-bandwidth memory interface.
6. The interposer of claim 3 , wherein the multiple mounting sites include one or more arrays of contacts forming a processor interface.
7. The interposer of claim 6 , wherein the interposer defines mounting sites forming first and second memory device interfaces, each mounting site including one or more arrays of contacts.
8. The interposer of claim 7 , wherein the contacts of the first and second memory device interfaces are connected through the first and second sets of multiple redistribution layers to contacts of the processor interface.
9. The interposer of claim 8 , wherein the contacts of the first memory device interface are connected to contacts of the processor interface through the first set of multiple redistribution layers; and wherein the contacts of the second memory device interface are connected to contacts of the processor interface through the second set of multiple redistribution layers.
10. The interposer of claim 8 , wherein contacts of at least one of the first and second memory device interfaces are connected to the second set of multiple redistribution layers through the vertical contacts extending through the core.
11. The interposer of claim 1 , wherein the passive circuit components are formed entirely within the dimensions of the core.
12. The interposer of claim 11 , wherein one or more of the passive components is coupled to at least one additional passive component.
13. The interposer of claim 1 , wherein the one or more circuit components comprise one or more active circuit components.
14. A method of forming an interposer for a microelectronic device assembly, comprising:
forming vertical interconnects extending through a semiconductor material forming an interposer core;
forming circuit components at least partially within the semiconductor material of the interposer core;
forming conductive traces over the interposer core;
forming a first set of multiple redistribution layers over a first side of the core;
forming a second set of multiple redistribution layers over a second side of the core opposite the first side.
15. The method of claim 14 , wherein an outermost redistribution layer of the first set of multiple redistribution layers is formed to include multiple arrays of contacts defining multiple microelectronic device mounting sites, each mounting site including at least one array of contacts.
16. The method of claim 14 , wherein forming the circuit components includes forming passive components, including, forming one or more passive components entirely within the semiconductor material of the interposer core.
17. The method of claim 14 , wherein forming the circuit components includes forming active components, and forming one or more active components includes a first body in the semiconductor material of the interposer core and forming a second body in a material extending above the interposer core and beneath the innermost redistribution layer of the first set of multiple redistribution layers.
18. The method of claim 14 , further comprising forming logic at least partially between the core and the first set of multiple redistribution layers.
19. The method of claim 18 , wherein forming logic comprises forming one or more logic devices partially in the core and partially in one or more materials extending above the core.
20. The method of claim 18 , wherein forming logic comprises forming one or more memory arrays.
21. The method of claim 20 , wherein the one or more memory arrays comprise at least one of DRAM, NOR flash, NAND flash, SRAM, and 3D X-point memory.
22. The method of claim 18 , wherein forming logic comprises forming an array of one or more of Field Programmable Gate Arrays (FPGAs), fuses, and anti-fuses.
23. A microelectronic device assembly, comprising:
an interposer including,
multiple mounting sites on a first surface of the interposer for multiple semiconductor device structures;
contact structures on a second surface of the interposer forming electrical connections to other structures;
a core comprising semiconductor material;
one or more circuit components formed at least partially in the semiconductor material of the core;
multiple vertical contacts extending through the core;
a first set of multiple redistribution layers formed one over a first side of the core; and
a second set of multiple redistribution layers formed over a second side of the core opposite the first side;
a first semiconductor device structure coupled to a first mounting site of the multiple mounting sites; and
a second semiconductor device structure coupled to a second mounting site of the multiple mounting sites.
24. The microelectronic device assembly of claim 23 , wherein the interposer defines a first communication channel between the first semiconductor device structure and the second semiconductor device structure.
25. The microelectronic device assembly of claim 23 , wherein the first semiconductor device structure comprises a semiconductor die.
26. The microelectronic device assembly of claim 23 , wherein the second semiconductor device structure comprises a memory device including multiple stacked and interconnected memory die.