IP Library Granted Patent US 11,360,899
Granted Patent B2
US 11,360,899 · App. 16/697,019 · Granted Jun 14, 2022

Fault tolerant data coherence in large-scale distributed cache systems

Inventors: Marjan Radi (San Jose, CA); Dejan Vucinic (San Jose, CA)
Assignee: Western Digital Technologies, Inc.
G06F12/0862G06F12/082G06F12/0802G06F12/0806G06F12/0817G06F12/0822G06F12/0828H04L67/1097H04L67/568G06F9/34G06F9/3824G06F2212/154G06F2212/602
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Quick Facts
Patent No.
US 11,360,899
App. No.
16/697,019
Granted
Jun 14, 2022
Kind
B2
Abstract

A programmable switch includes a plurality of ports for communication with devices on a network. Circuitry of the programmable switch is configured to receive a cache line request from a client on the network to obtain a cache line for performing an operation by the client. A port is identified for communicating with a memory device storing the cache line. The memory device is one of a plurality of memory devices used for a distributed cache. The circuitry is further configured to update a cache directory for the distributed cache based on the cache line request, and send the cache line request to the memory device using the identified port. In one aspect, it is determined whether the cache line request is for modifying the cache line.

Claims (82)

1. A programmable switch, comprising:

a plurality of ports for communication with devices on a network; and

circuitry configured to:

receive a cache line request from a client on the network to obtain a cache line for performing an operation by the client;

identify a port of the plurality of ports for communicating with a memory device storing the cache line, wherein the memory device is one of a plurality of memory devices used for a distributed cache;

update a cache directory stored at the programmable switch for the distributed cache based on the cache line request; and

send the cache line request to the memory device using the identified port.

2. The programmable switch of claim 1 , wherein the circuitry is further configured to:

receive an additional cache line request from a different client to obtain the cache line;

determine a status of the cache line as being in progress of being modified by the client based on the updated cache directory; and

send a new request for a modified version of the cache line to the client to return the modified version of the cache line to the memory device.

3. The programmable switch of claim 1 , wherein the circuitry is further configured to:

determine whether the cache line request is for modifying the cache line; and

in response to determining that the cache line request is for modifying the cache line, update a version number for the cache line in the cache directory.

4. The programmable switch of claim 1 , wherein the cache line request follows a custom packet format including one or more fields indicating a permission level for the operation to be performed by the client.

5. The programmable switch of claim 1 , wherein the cache line request follows a custom packet format including one or more fields indicating that the cache line request is a cache line memory message.

6. The programmable switch of claim 1 , wherein the programmable switch forms part of a Software Defined Networking (SDN).

7. The programmable switch of claim 1 , wherein the cache directory is configured to include network addresses for multiple devices on the network that store data corresponding to a memory address for the cache line.

8. The programmable switch of claim 1 , wherein the circuitry is further configured to send an indication of the cache directory update to at least one of another programmable switch on the network and a Software Defined Networking (SDN) controller to update one or more mirrored cache directories.

9. The programmable switch of claim 1 , wherein the circuitry is further configured to:

receive a request from a controller on the network for version numbers for cache lines that have been modified; and

send the controller version numbers for the cache lines that have been modified.

10. A method of providing a distributed cache, the method comprising:

receiving a cache line request from a client on a network to obtain a cache line from a memory device of a plurality of memory devices used for a distributed cache;

determining whether the cache line request is for modifying the cache line;

in response to determining that the cache line request is for modifying the cache line, updating a version number for the cache line in a cache directory for the distributed cache; and

sending the cache line request to the memory device.

11. The method of claim 10 , further comprising:

receiving an additional cache line request from a different client to obtain the cache line;

determining a status of the cache line as being in progress of being modified by the client based on the updated cache directory; and

sending a new request for a modified version of the cache line to the client to return the modified version of the cache line to the memory device.

12. The method of claim 10 , wherein the cache line request follows a custom packet format including one or more fields indicating a permission level for determining whether the cache line is to be modified or read by the client.

13. The method of claim 10 , wherein the cache line request follows a custom packet format including one or more fields indicating that the cache line request is a cache line memory message.

14. The method of claim 10 , wherein the cache directory is updated by a programmable switch that forms part of a Software Defined Networking (SDN).

15. The method of claim 10 , wherein the cache directory is configured to include network addresses for multiple devices on the network that store data corresponding to a memory address for the cache line.

16. The method of claim 10 , further comprising sending an indication of the cache directory update to at least one of a programmable switch on the network and a Software Defined Networking (SDN) controller to update one or more mirrored cache directories.

17. The method of claim 10 , further comprising:

receiving a request from a controller on the network for version numbers for cache lines that have been modified; and

sending version numbers to the controller for the cache lines that have been modified.

18. The method of claim 10 , wherein a status of the cache line in the cache directory indicates that multiple clients on the network have a shared read-only permission level.

19. A non-transitory computer readable medium storing computer-executable instructions, wherein when the computer-executable instructions are executed by circuitry of a programmable switch, the computer-executable instructions cause the circuitry to:

receive a cache line request from a client to obtain a cache line for performing an operation by the client;

identify a port from among a plurality of ports of the programmable switch for communicating with a memory device storing the cache line, wherein the memory device is one of a plurality of memory devices used for a distributed cache;

update a cache directory for the distributed cache based on the cache line request;

send an indication of the cache directory update to at least one of another programmable switch on the network and a Software Defined Networking (SDN) controller to update one or more mirrored cache directories; and

send the cache line request to the memory device using the identified port.

20. A system for a distributed cache, the system comprising:

a plurality of memory devices storing at least part of the distributed cache;

a first programmable switch in communication with one or more of the plurality of memory devices, the first programmable switch including first circuitry; and

a second programmable switch in communication with the first programmable switch and with one or more of the plurality of memory devices, the second programmable switch including second circuitry; and

wherein the first circuitry and the second circuitry are configured to update respective cache directories for the distributed cache based on cache line requests received by at least one of the first programmable switch and the second programmable switch.

21. The system of claim 20 , wherein the first circuitry is further configured to send to the second programmable switch an indication of an update to the cache directory of the first programmable switch.

22. The system of claim 21 , wherein the second circuitry is further configured to update the cache directory of the second programmable switch in response to receiving the indication of the update to the cache directory of the first programmable switch.

23. The system of claim 20 , wherein the first circuitry is further configured to send an indication of an update to the cache directory of the first programmable switch to a Software Defined Networking (SDN) controller.

24. The system of claim 20 , wherein the first circuitry is further configured to:

receive a request from a controller in communication with the first programmable switch for version numbers for cache lines that have been modified; and

send the controller version numbers for the cache lines that have been modified.

25. The system of claim 20 , wherein the first circuitry is further configured to:

receive a cache line request from a client to obtain a cache line for performing an operation by the client;

identify a port from among a plurality of ports of the first programmable switch for communicating with a memory device of the plurality of memory devices that stores the cache line;

update the cache directory of the first programmable switch based on the cache line request; and

send the cache line request to the memory device using the identified port.

26. The system of claim 25 , wherein the first circuitry is further configured to:

receive an additional cache line request from a different client to obtain the cache line;

determine a status of the cache line as being in progress of being modified by the client based on the updated cache directory; and

send a new request for a modified version of the cache line to the client to return the modified version of the cache line to the memory device.

27. The system of claim 25 , wherein the first circuitry is further configured to:

determine whether the cache line request is for modifying the cache line; and

in response to determining that the cache line request is for modifying the cache line, update a version number for the cache line in the cache directory of the first programmable switch.

28. The system of claim 25 , wherein the cache line request follows a custom packet format including one or more fields indicating a permission level for determining whether the cache line is to be modified or read by the client.

29. The system of claim 25 , wherein the cache line request follows a custom packet format including one or more fields indicating that the cache line request is a cache line memory message.

30. The system of claim 20 , wherein each cache directory of the first programmable switch and the second programmable switch is configured to include network addresses for multiple devices that store data corresponding to a memory address for a cache line.

31. A programmable switch, comprising:

a plurality of ports for communication with devices on a network; and

means for:

receiving a cache line request from a client on the network to obtain a cache line for performing an operation by the client;

identifying a port of the plurality of ports for communicating with a memory device storing the cache line, wherein the memory device is one of a plurality of memory devices used for a distributed cache;

updating a cache directory for the distributed cache based on the cache line request;

sending the cache line request to the memory device using the identified port;

receiving an additional cache line request from a different client to obtain the cache line;

determining a status of the cache line as being in progress of being modified by the client based on the updated cache directory; and

sending a new request for a modified version of the cache line to the client to return the modified version of the cache line to the memory device.

Assignments (5)
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052025 FRAME 0088 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058965/0699 →
SECURITY INTEREST Recorded Feb 26, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052025/0088 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 26, 2019
From: RADI, MARJAN; VUCINIC, DEJAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 051124/0634 →
Continuity (2)
Provisional Application 62842959 · May 3, 2019
Related Publication 20200351370A1 · Nov 5, 2020
Cited By (1)
US 12,379,951