Noise cancelling circuit and data transmission circuit
View Patent ↗A noise cancelling circuit includes: a first parallel-serial conversion circuit which converts inputted 2N-bit parallel data into serial data; an inverting circuit which inverts one of odd-numbered bits and even-numbered bits included in the inputted 2N-bit parallel data; a second parallel-serial conversion circuit which converts, into serial data, parallel data outputted by the inverting circuit and parallel data of the other one of the odd-numbered bits and the even-numbered bits included in the inputted 2N-bit parallel data which were not inverted; a first buffer which receives output data of the first parallel-serial conversion circuit; and a second buffer which receives output data of the second parallel-serial conversion circuit.
1. A noise cancelling circuit, comprising:
a first parallel-serial conversion circuit which converts 2N-bit parallel data into serial data in synchronization with a clock signal, where N is a natural number of 1 or more;
an inverting circuit which inverts one of odd-numbered bits and even-numbered bits included in the 2N-bit parallel data;
a second parallel-serial conversion circuit which converts, into serial data in synchronization with the clock signal, parallel data outputted by the inverting circuit and parallel data of the other one of the odd-numbered bits and the even-numbered bits included in the 2N-bit parallel data which were not inverted;
a first buffer which receives output data of the first parallel-serial conversion circuit; and
a second buffer which receives output data of the second parallel-serial conversion circuit, wherein
the first parallel-serial conversion circuit and the second parallel-serial conversion circuit are formed using substantially a same kind of circuit,
the first buffer and the second buffer are formed using substantially a same kind of circuit, and
the first buffer and the second buffer are connected to a common power source and connected to a common ground.
2. The noise cancelling circuit according to claim 1 , wherein
an output terminal of the second buffer is connected with a same kind of load as a load of an output terminal of the first buffer.
3. The noise cancelling circuit according to claim 1 , further comprising
a capacitor for smoothing power source noise, the capacitor being connected between the common power source and the common ground connected to the first buffer and the second buffer.
4. A data transmission circuit, comprising:
the noise cancelling circuit according to claim 1 ;
a third buffer connected to an output terminal of the first buffer included in the noise cancelling circuit, the third buffer outputting a differential signal; and
a fourth buffer connected to an output terminal of the second buffer included in the noise cancelling circuit, the fourth buffer being formed using substantially a same kind of circuit as a circuit of the third buffer.
5. The data transmission circuit according to claim 4 , wherein
the third buffer and the fourth buffer are connected to a common power source and connected to a common ground.
6. A data transmission circuit, comprising:
a plurality of noise cancelling circuits each serving as the noise cancelling circuit according to claim 1 ;
a fifth buffer which receives a plurality of pieces of serial data outputted from the first parallel-serial conversion circuits respectively included in the plurality of noise cancelling circuits, the fifth buffer outputting a multilevel signal; and
a sixth buffer which receives a plurality of pieces of serial data outputted from the second parallel-serial conversion circuits respectively included in the plurality of noise cancelling circuits, the sixth buffer outputting a multilevel signal, wherein
an output terminal of the sixth buffer is connected with a same kind of load as a load of an output terminal of the fifth buffer.
7. A noise cancelling circuit, comprising:
a first parallel-serial conversion circuit which converts N-bit parallel data into serial data in synchronization with a clock signal, where N is an odd number of 1 or more;
a selector section which receives the N-bit parallel data and which outputs parallel data by alternately switching in an update cycle of the N-bit parallel data between a mode in which inverted odd-numbered bits and non-inverted even-numbered bits with respect to the inputted N-bit parallel data are outputted and a mode in which non-inverted odd-numbered bits and inverted even-numbered bits with respect to the inputted N-bit parallel data are outputted;
a second parallel-serial conversion circuit which converts the parallel data outputted by the selector section into serial data in synchronization with the clock signal;
a first buffer which receives output data of the first parallel-serial conversion circuit; and
a second buffer which receives output data of the second parallel-serial conversion circuit, wherein
the first parallel-serial conversion circuit and the second parallel-serial conversion circuit are formed using substantially a same kind of circuit,
the first buffer and the second buffer are formed using substantially a same kind of circuit, and
the first buffer and the second buffer are connected to a common power source and connected to a common ground.
8. The noise cancelling circuit according to claim 7 , wherein
an output terminal of the second buffer is connected with a same kind of load as a load of an output terminal of the first buffer.
9. The noise cancelling circuit according to claim 7 , further comprising
a capacitor for smoothing power source noise, the capacitor being connected between the common power source and the common ground connected to the first buffer and the second buffer.
10. A data transmission circuit, comprising:
the noise cancelling circuit according to claim 7 ;
a third buffer connected to an output terminal of the first buffer included in the noise cancelling circuit, the third buffer outputting a differential signal; and
a fourth buffer connected to an output terminal of the second buffer included in the noise cancelling circuit, the fourth buffer being formed using substantially a same kind of circuit as a circuit of the third buffer.
11. The data transmission circuit according to claim 10 , wherein
the third buffer and the fourth buffer are connected to a common power source and connected to a common ground.
12. A data transmission circuit, comprising:
a plurality of noise cancelling circuits each serving as the noise cancelling circuit according to claim 7 ;
a fifth buffer which receives a plurality of pieces of serial data outputted from the first parallel-serial conversion circuits respectively included in the plurality of noise cancelling circuits, the fifth buffer outputting a multilevel signal; and
a sixth buffer which receives a plurality of pieces of serial data outputted from the second parallel-serial conversion circuits respectively included in the plurality of noise cancelling circuits, the sixth buffer outputting a multilevel signal, wherein
an output terminal of the sixth buffer is connected with a same kind of load as a load of an output terminal of the fifth buffer.