IP Library Granted Patent US 11,294,628
Granted Patent B2
US 11,294,628 · App. 16/702,099 · Granted Apr 5, 2022

Processing element and processing system

Inventor: Jae-Hyeok Jang (Gyeonggi-do, KR)
Assignee: SK hynix Inc.
G06F7/4925G06F7/50G06F7/5443G06N3/063G06F2207/4824
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Quick Facts
Patent No.
US 11,294,628
App. No.
16/702,099
Granted
Apr 5, 2022
Kind
B2
Abstract

A processing element may include a pre-processing circuit configured to receive and filter a feature and a weight and output a filtered feature and a filtered weight; and an accumulation circuit configured to accumulate a value of the filtered feature, wherein the pre-processing circuit comprises: a sign conversion circuit configured to change a sign of the feature and a sign of the weight when the weight having a value of −1; and a zero filtering circuit configured to change a value of the weight to 0 when the feature having a value of 0.

Claims (65)

1. A processing element comprising:

a pre-processing circuit configured to receive and filter a feature and a weight and output a filtered feature and a filtered weight; and

an accumulation circuit configured to accumulate a value of the filtered feature,

wherein the pre-processing circuit comprises:

a sign conversion circuit configured to change a sign of the feature and a sign of the weight when the weight has a value of −1; and

a zero filtering circuit configured to change a value of the weight to 0 when the feature has a value of 0.

2. The processing element of claim 1 , wherein the accumulation circuit accumulates the value of the filtered feature when the value of the filtered feature is 1.

3. The processing element of claim 1 , wherein the feature and the weight received by to the pre-processing circuit are processed by the sign conversion circuit, and the feature and the weight processed by the sign conversion circuit are processed by the zero filtering circuit, so that the filtered feature and the filtered weight are generated.

4. The processing element of claim 1 , wherein the feature and the weight received by to the pre-processing circuit are processed by the zero filtering circuit, and the feature and the weight processed by the zero filtering circuit are processed by the sign conversion circuit, so that the filtered feature and the filtered weight are generated.

5. The processing element of claim 1 , wherein the zero filtering circuit changes a value of the feature to 0 when a value of the weight is 0.

6. The processing element of claim 1 , wherein the accumulation circuit comprises:

an adder configured to add a cumulative value and the value of the filtered feature; and

a register configured to store an addition result of the adder as the cumulative value when the filtered weight is 1.

7. The processing element of claim 1 , wherein the weight received by to the pre-processing circuit has a value of 1, 0, or −1.

8. A processing element comprising:

a pre-processing circuit configured to receive and filter a feature and a weight and output a filtered feature and a filtered weight; and

an accumulation circuit configured to accumulate a value of the filtered feature,

wherein the pre-processing circuit comprises:

a sign conversion circuit configured to change a sign of the feature and a sign of the weight when the weight has a value of 1; and

a zero filtering circuit configured to change a value of the weight to 0 when the feature having a value of 0.

9. The processing element of claim 8 , wherein the accumulation circuit accumulates the value of the filtered feature when the value of the filtered weight is −1.

10. The processing element of claim 8 , wherein the zero filtering circuit changes a value of the feature to 0 when a value of the weight is 0.

11. A processing system comprising:

a cache memory configured to store a feature and a weight; and

a processing element configured to operate the feature and the weight transferred from the cache memory,

wherein the processing element comprises:

a pre-processing circuit configured to receive and filter the feature and the weight and output a filtered feature and a filtered weight; and

an accumulation circuit configured to accumulate a value of the filtered feature, and

the pre-processing circuit comprises:

a sign conversion circuit configured to change a sign of the feature and a sign of the weight when the weight has a value of −1; and

a zero filtering circuit configured to change a value of the weight to 0 when the feature has a value of 0.

12. The processing system of claim 11 , wherein the accumulation circuit accumulates the value of the filtered feature when the value of the filtered feature has a value of 1.

13. The processing system of claim 11 , further comprising:

a host interface for communication with a host;

a memory configured to store data;

a memory interface configured to access the data of the memory;

a bus interface configured to provide interfacing among the host interface, a memory interface, and the cache memory; and

a post-processor configured to post-process an operation result of the processing element.

14. The processing system of claim 11 , wherein the feature and the weight received by to the pre-processing circuit are processed by the sign conversion circuit, and the feature and the weight processed by the sign conversion circuit are processed by the zero filtering circuit, so that the filtered feature and the filtered weight are generated.

15. The processing system of claim 11 , wherein the feature and the weight received by to the pre-processing circuit are processed by the zero filtering circuit, and the feature and the weight processed by the zero filtering circuit are processed by the sign conversion circuit, so that the filtered feature and the filtered weight are generated.

16. The processing system of claim 11 , wherein the zero filtering circuit changes a value of the feature to 0 when value of the weight is 0.

17. The processing system of claim 11 , wherein the accumulation circuit comprises:

an adder configured to add a cumulative value and the value of the filtered feature; and

a register configured to store an addition result of the adder as the cumulative value when the filtered weight has a value of 1.

18. The processing system of claim 11 , wherein the weight inputted to the pre-processing circuit has a value of 1, 0, or −1.

19. A processing system comprising:

a cache memory configured to store a feature and a weight; and

a processing element configured to operate the feature and the weight transferred from the cache memory,

wherein the processing element comprises:

a pre-processing circuit configured to receive and filter the feature and the weight and output a filtered feature and a filtered weight; and

an accumulation circuit configured to accumulate a value of the filtered feature, and

the pre-processing circuit comprises:

a sign conversion circuit configured to change a sign of the feature and a sign of the weight when the weight has a value of 1; and

a zero filtering circuit configured to change a value of the weight to 0 when the feature has a value of 0.

20. The processing system of claim 19 , wherein the accumulation circuit accumulates the value of the filtered feature when the value of the filtered weight has a value of −1.

21. The processing system of claim 19 , further comprising:

a host interface for communication with a host;

a memory configured to store data;

a memory interface configured to access the data of the memory;

a bus interface configured to provide interfacing among the host interface, the memory interface, and the cache memory; and

a post-processor configured to post-process an operation result of the processing element.

22. The processing system of claim 19 , wherein the zero filtering circuit changes a value of the feature to 0 when the weight has a value of 0.

23. The processing system of claim 19 , wherein the accumulation circuit comprises:

an adder configured to add a cumulative value and the value of the filtered feature; and

a register configured to store an addition result of the adder as the cumulative value when the filtered weight having a value of −1.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2024
From: SK HYNIX INC.
To: MIMIRIP LLC
Reel/Frame 067335/0246 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 3, 2019
From: JANG, JAE-HYEOK
To: SK HYNIX INC.
Reel/Frame 051171/0234 →