MULTIPLE UPLINK PORT DEVICES
A device is provided with two or more uplink ports to connect the device via two or more links to one or more sockets, where each of the sockets includes one or more processing cores, and each of the two or more links is compliant with a particular interconnect protocol. The device further includes I/O logic to identify data to be sent to the one or more processing cores for processing, determine an affinity attribute associated with the data, and determine which of the two or more links to use to send the data to the one or more processing cores based on the affinity attribute.
1 . An apparatus comprising:
a device comprising two or more uplink ports to connect the device via two or more links to one or more sockets, wherein each of the sockets comprises one or more processing cores, and each of the two or more links is compliant with a particular interconnect protocol; and
I/O logic to:
identify data to be sent to the one or more processing cores for processing;
determine an affinity attribute associated with the data; and
determine which of the two or more links to use to send the data to the one or more processing cores based on the affinity attribute.
2 . The apparatus of claim 1 , wherein the one or more sockets comprise two or more sockets, and the two or more uplink ports each connect to a respective one of two or more sockets.
3 . The apparatus of claim 2 , further comprising partition logic to present the device as two or more logical device instances to the two or more sockets, wherein each of the logical device instances corresponds to a respective one of the two or more sockets and connect via a respective one of the two or more uplink ports.
4 . The apparatus of claim 1 , wherein the particular interconnect protocol is adapted for devices with a single uplink port.
5 . The apparatus of claim 1 , wherein the I/O logic is further to identify a request received at the device, the data is to be sent in response to the request, and the affinity attribute corresponds to the request.
6 . The apparatus of claim 5 , wherein the affinity attribute comprises a requester identifier, the I/O logic is further to identify that a particular one of the two or more uplink ports corresponds to the requester identifier, and send the data on the particular uplink port based on the requester identifier.
7 . The apparatus of claim 6 , wherein the requester identifier identifies a particular one of the processing cores.
8 . The apparatus of claim 5 , wherein the request is received on a particular one of the two or more uplink ports, and the data is to be sent on the particular uplink port based on the request being received on the particular uplink port.
9 . The apparatus of claim 5 , wherein the request comprises a work descriptor from a driver of the device, the affinity attribute comprises a hint inserted in the work descriptor by the driver, and the I/O logic is to determine that the data is to be sent on a particular one of the two or more uplink ports based on the hint.
10 . The apparatus of claim 1 , wherein the two or more uplink ports are to connect to a single socket connected by two or more links.
11 . The apparatus of claim 1 , further comprising power management logic to:
determine a link state transition to a particular power state for a particular one of the two or more links corresponding to sending of the data; and
cause another one of the two or more links to also transition to the particular power state based on the link state transition of the particular link.
12 . The apparatus of claim 1 , wherein the particular interconnect protocol comprises a Peripheral Component Interconnect Express (PCIe)-based protocol.
13 . A system comprising:
memory;
a processor;
an operating system;
a first instance of a particular driver, wherein the particular driver is for a device type and the first instance of the particular driver is assigned to a first interconnect link to connect the processor to a particular instance of the device;
a second instance of the particular driver, wherein the second instance of the particular driver is assigned to a second interconnect link to connect the processor to the particular instance of the device, wherein the particular instance of the device comprises two or more uplink ports, the first instance of the particular driver is designated as a principal instance, and the operating system communicates with the particular instance of the device using the first instance of the particular driver.
14 . The system of claim 13 , wherein the processor comprises a plurality of sockets, each of the plurality of sockets comprises one or more processing cores, the first interconnect link connects the particular instance of the device to a first one of the plurality of sockets, and the second interconnect link connects the particular instance of the device to a second one of the plurality of sockets.
15 . The system of claim 14 , wherein the first instance of the particular driver is to:
determine that a work request corresponds to a particular one of the plurality of sockets;
append a hint to the work request to identify that data generated by the particular instance of the device for the work request is to be sent on a particular one of the two or more uplink ports; and
send the work request with the hint to the particular instance of the device.
16 . A system comprising:
a processor comprising a plurality of sockets, wherein each socket comprises one or more processing cores and the plurality of sockets are interconnected by one or more interprocessor links; and
a particular device comprising two or more uplink ports to connect the particular device via two or more links to two or more of the plurality of sockets, wherein each of the two or more links is compliant with a particular interconnect protocol and the particular device comprises port policy logic to:
identify data to be sent to the processor for processing; and
determine which of the two or more links to use to send the data according to one or more policies, wherein the one or more policies are to attempt to minimize routing of the data over the one or more interprocessor links.
17 . The system of claim 16 , wherein each of the plurality of sockets is connected to a respective local memory block, the data comprises a write request to a particular one of the local memory blocks, and the policy is to attempt to direct the data to a particular one of the two or more links connecting the particular device to the socket directly connected to the particular local memory block.
18 . The system of claim 16 , further comprising another device comprising a single uplink port, wherein the other device connects to a particular one of the sockets via a link.
19 . The system of claim 16 , further comprising an operating system and one or more drivers for the particular device.
20 . The system of claim 16 , wherein the particular interconnect protocol comprises a Peripheral Component Interconnect Express (PCIe)-based protocol and the one or more interprocessor links use an UltraPath Interconnect (UPI)-based protocol.