Enhanced bonding between III-V material and oxide material
When III-V semiconductor material is bonded to an oxide material, water molecules can degrade the bonding if they become trapped at the interface between the III-V material and the oxide material. Because water molecules can diffuse readily through oxide material, and may not diffuse as readily through III-V material or through silicon, forcing the III-V material against the oxide material can force water molecules at the interface into the oxide material and away from the interface. Water molecules present at the interface can be forced during manufacturing through vertical channels in a silicon layer into a buried oxide layer thereby to enhance bonding between the III-V material and the oxide material. Water molecules can be also forced through lateral channels in the oxide material, past a periphery of the III-V material, and, through diffusion, out of the oxide material into the atmosphere.
1. An integrated circuit comprising:
a substrate;
a silicon layer comprising channels that are etched into the silicon laver;
an oxide layer disposed on the silicon layer such that oxide material of the oxide layer fills the channels to form filled channels and forms a bonding surface of the oxide material on the filled channels; and
a III-V semiconductor layer disposed on the bonding surface of the oxide layer, wherein during manufacturing water molecules present between the III-V semiconductor layer and the oxide layer diffuse away from the III-V semiconductor layer through the bonding surface and through the filled channels to increase bonding between the III-V semiconductor layer and the oxide layer.
2. The integrated circuit of claim 1 , wherein the filled channels are filled lateral channels that extend laterally from an interior of the silicon laver.
3. The integrated circuit of claim 1 , wherein the filled channels are positioned in a repeating pattern around a periphery of the silicon layer.
4. The integrated circuit of claim 2 , wherein the silicon layer further includes filled vertical channels through which water diffuses.
5. The integrated circuit of claim 4 , wherein the water molecules are forced during manufacturing into the filled vertical channels away from the III-V semiconductor layer.
6. The integrated circuit of claim 5 , wherein the filled vertical channels are etched in a repeating pattern in the silicon layer.
7. The integrated circuit of claim 4 , wherein the filled vertical channels are perpendicular to a plane of the silicon layer, and wherein the filled lateral channels extend laterally along the plane of the silicon layer.
8. The integrated circuit of claim 1 , wherein the bonding surface is planarized by polishing during manufacturing.
9. The integrated circuit of claim 8 , wherein the III-V semiconductor layer is included on a III-V semiconductor chip.
10. The integrated circuit of claim 9 , wherein during manufacturing the III-V semiconductor chip is forced against the oxide layer to diffuse the water molecules through the bonding surface and through the filled channels.
11. The integrated circuit of claim 1 , wherein the silicon layer is etched to a depth to form the channels.
12. The integrated circuit of claim 11 , wherein the silicon layer comprises waveguides formed from etching the silicon layer.
13. The integrated circuit of claim 12 , wherein the waveguides are etched at another depth different from the depth to which the channels are etched in the silicon layer.
14. The integrated circuit of claim 12 , wherein the waveguides and the channels are etched during manufacturing at a same depth in the silicon layer.
15. The integrated circuit of claim 1 , wherein the water molecules are forced through the bonding surface and through the filled channels using ambient pressure and temperature greater than room temperature.
16. The integrated circuit of claim 1 , wherein the water molecules are forced through the bonding surface and through filled channels using a vacuum at greater than room temperature.
17. The integrated circuit of claim 1 , wherein the substrate comprises silicon.
18. The integrated circuit of claim 1 , wherein the integrated circuit comprises a buried oxide layer.
19. The integrated circuit of claim 1 , wherein the oxide material is silicon dioxide.
20. The integrated circuit of claim 1 , wherein the III-V semiconductor layer comprises indium phosphide.