IP Library Granted Patent US 11,355,654
Granted Patent B2
US 11,355,654 · App. 16/707,975 · Granted Jun 7, 2022

Tri-layer semiconductor stacks for patterning features on solar cells

Inventors: Kieran Mark Tracy (San Jose, CA); David D. Smith (Campbell, CA); Venkatasubramani Balu (Santa Clara, CA); Asnat Masad (Mountain View, CA); Ann Waldhauer (La Honda, CA)
Assignee: SunPower Corporation
H01L31/022441H01L31/02363H01L31/022425H01L31/022458H01L31/035281H01L31/0516H01L31/0682H01L31/0745H01L31/0747H01L31/18H01L31/1804H01L31/202Y02E10/50Y02E10/546Y02E10/547Y02E10/548
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Quick Facts
Patent No.
US 11,355,654
App. No.
16/707,975
Granted
Jun 7, 2022
Kind
B2
Abstract

Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.

Claims (61)

1. A solar cell, comprising:

a first thin dielectric layer disposed on a back surface of a substrate;

a semiconductor structure disposed on the first thin dielectric layer, wherein the semiconductor structure comprises a stack of three or more distinct semiconductor layers;

a second thin dielectric layer disposed on the back surface of the substrate;

a polycrystalline silicon emitter region disposed on the second thin dielectric layer;

a third thin dielectric layer disposed directly between the semiconductor structure and the polycrystalline silicon emitter region, wherein the third thin dielectric layer is at least partially sloped between the semiconductor structure and the polycrystalline silicon emitter region;

an insulator layer disposed on the semiconductor structure, wherein at least a portion of the polycrystalline silicon emitter region is disposed on the insulator layer;

a first conductive contact structure disposed on the semiconductor structure, wherein the first conductive contact structure is disposed through the insulator layer; and

a second conductive contact structure disposed on the polycrystalline silicon emitter region, wherein the polycrystalline silicon emitter region overlaps the semiconductor structure.

2. The solar cell of claim 1 , wherein the stack of the semiconductor structure is a tri-layer semiconductor stack.

3. The solar cell of claim 1 , wherein the stack of the semiconductor structure comprises:

a first semiconductor layer disposed on the first thin dielectric layer;

a P-type semiconductor layer disposed on the first semiconductor layer; and

a third semiconductor layer disposed on the P-type semiconductor layer.

4. The solar cell of claim 1 , wherein the first, second and third thin dielectric layer comprise silicon dioxide.

5. The solar cell of claim 1 , wherein a second portion of the back surface comprises a texturized surface.

6. The solar cell of claim 1 , wherein the polycrystalline silicon emitter region is N-type.

7. The solar cell of claim 1 , wherein the first and second conductive contact structures each comprises an aluminum-based metal seed layer disposed on the semiconductor structure and the polycrystalline silicon emitter region, respectively, and each further comprises a metal layer disposed on the aluminum-based metal seed layer.

8. The solar cell of claim 1 , further comprising:

a fourth thin dielectric layer disposed on a light-receiving surface of the substrate;

a polycrystalline silicon layer disposed on the fourth thin dielectric layer; and

an anti-reflective coating (ARC) layer disposed on the polycrystalline silicon layer.

9. A solar cell, comprising:

a first thin dielectric layer disposed on a back surface of a substrate;

a semiconductor stack disposed on the first thin dielectric layer, wherein the semiconductor stack comprises a stack of three or more distinct semiconductor layers;

a second thin dielectric layer disposed on the back surface of the substrate;

a polycrystalline silicon emitter region disposed on the second thin dielectric layer;

a third thin dielectric layer disposed directly between the semiconductor stack and the polycrystalline silicon emitter region;

an insulator layer disposed on the semiconductor stack, wherein at least a portion of the polycrystalline silicon emitter region is disposed on the insulator layer;

a first conductive contact structure disposed on the semiconductor stack, wherein the first conductive contact structure is disposed through the insulator layer; and

a second conductive contact structure disposed on the polycrystalline silicon emitter region, wherein the polycrystalline silicon emitter region overlaps the semiconductor stack.

10. The solar cell of claim 9 , wherein the stack of the semiconductor stack is a tri-layer semiconductor stack.

11. The solar cell of claim 9 , wherein the stack of the semiconductor stack comprises:

a first semiconductor layer disposed on the first thin dielectric layer;

a P-type semiconductor layer disposed on the first semiconductor structure; and

a third semiconductor layer disposed on the P-type semiconductor layer.

12. The solar cell of claim 9 , wherein the first, second and third thin dielectric layer comprise silicon dioxide.

13. The solar cell of claim 9 , wherein the polycrystalline silicon emitter region is N-type.

14. The solar cell of claim 9 , wherein the first and second conductive contact structures each comprises an aluminum-based metal seed layer disposed on the semiconductor stack and the polycrystalline silicon emitter region, respectively, and each further comprises a metal layer disposed on the aluminum-based metal seed layer.

15. The solar cell of claim 9 , further comprising:

a fourth thin dielectric layer disposed on a light-receiving surface of the substrate;

a polycrystalline silicon layer disposed on the fourth thin dielectric layer; and

an anti-reflective coating (ARC) layer disposed on the polycrystalline silicon layer.

16. A solar cell, comprising:

a first thin dielectric layer disposed on a back surface of a substrate;

a first semiconductor layer disposed on the first thin dielectric layer, the first semiconductor layer comprising an outermost edge;

a second semiconductor layer disposed on the first semiconductor layer, the second semiconductor layer comprising a sloped outermost edge; and

a third semiconductor layer disposed on the second semiconductor layer, the third semiconductor layer comprising a third outermost edge, wherein the third outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer;

a second thin dielectric layer disposed on the back surface of the substrate;

a polycrystalline silicon emitter region disposed on the second thin dielectric layer;

a third thin dielectric layer disposed on the first, second and third outermost edges;

an insulator layer disposed on the third semiconductor layer, wherein at least a portion of the polycrystalline silicon emitter region is disposed on the insulator layer;

a first conductive contact structure disposed on the third semiconductor layer, wherein the first conductive contact structure is disposed through the insulator layer; and

a second conductive contact structure disposed on the polycrystalline silicon emitter region, wherein the polycrystalline silicon emitter region overlaps the first, second and third semiconductor layers.

17. The solar cell of claim 16 , wherein the second semiconductor layer comprises a P-type semiconductor layer.

18. The solar cell of claim 16 , wherein the polycrystalline silicon emitter region is N-type.

19. The solar cell of claim 16 , wherein the first and second conductive contact structures each comprises an aluminum-based metal seed layer disposed on the third semiconductor layer and polycrystalline silicon emitter region, respectively, and each further comprises a metal layer disposed on the aluminum-based metal seed layer.

20. The solar cell of claim 16 , further comprising:

a fourth thin dielectric layer disposed on a light-receiving surface of the substrate;

a polycrystalline silicon layer disposed on the fourth thin dielectric layer; and

an anti-reflective coating (ARC) layer disposed on the polycrystalline silicon layer.

Assignments (4)
SECURITY INTEREST Recorded Jun 27, 2024
From: MAXEON SOLAR PTE. LTD.
To: DB TRUSTEES (HONG KONG) LIMITED
Reel/Frame 067924/0062 →
SECOND LIEN SECURITY INTEREST AGREEMENT Recorded Jun 26, 2024
From: MAXEON SOLAR PTE. LTD
To: DB TRUSTEES (HONG KONG) LIMITED
Reel/Frame 071343/0553 →
SECURITY INTEREST Recorded Jun 5, 2024
From: MAXEON SOLAR PTE. LTD.
To: DB TRUSTEES (HONG KONG) LIMITED
Reel/Frame 067637/0598 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2023
From: SUNPOWER CORPORATION
To: MAXEON SOLAR PTE. LTD.
Reel/Frame 062699/0875 →