Shared comparator for charge pumps

1. A power converter circuit including:

(a) at least one set of N series switches where N≥2, each set configured as one of M charge pump legs where M≥1, wherein each pair of adjacent series switches in each charge pump leg defines a stack-node V CXM located between the adjacent series switches, where N−1≥X>1;

(b) at least one voltage scaling circuit, each coupled to a corresponding stack-node V CXM and configured to output a voltage proportional to a voltage at the corresponding stack-node V CXM ;

(c) at least one multiplexor, each having (1) at least one input, each input coupled to the output of a corresponding one of the at least one voltage scaling circuit, and (2) at least one output; and

(d) at least one comparator circuit, each having a first input coupled to a corresponding output of one of the at least one multiplexor, and a second input coupled to a reference signal, and configured to output a signal indicative of a difference between a selected input to the multiplexor and the reference signal;

wherein the number of comparator circuits is less than (N−1)×M.

2. The invention of claim 1 , wherein at least one voltage scaling circuit includes a voltage divider comprising first and second series-connected resistors coupled between the corresponding stack-node V CXM and circuit ground.

3. The invention of claim 2 , wherein the voltage divider includes at least one series switch configured to make the voltage divider selectably isolatable.

4. The invention of claim 1 , wherein the reference signal is generated by a voltage divider comprising first and second series-connected resistors coupled between a supply voltage and circuit ground.

5. The invention of claim 4 , wherein the reference signal is adjustable in value.

6. The invention of claim 4 , wherein the supply voltage is derived from an isolated voltage scaling circuit for a selected stack-node V CXM .

7. The invention of claim 1 , wherein at least one of the at least one comparator circuit includes latch circuitry coupled to the output of the comparator circuit for capturing a status for multiple stack-nodes V CXM .

8. The invention of claim 1 , wherein all stack-nodes V CXM are coupled to one multiplexor, and the one multiplexor is coupled to one comparator circuit.

9. The invention of claim 1 , wherein one or more stack-nodes V CXM designated by the same X value but different M values are coupled to one respective multiplexor, and the one respective multiplexor is coupled to one corresponding comparator circuit.

10. The invention of claim 1 , wherein one or more stack-nodes V CXM designated by the same M value but different X values are coupled to one respective multiplexor, and the one respective multiplexor is coupled to one corresponding comparator circuit.

11. The invention of claim 1 , wherein:

(a) a first subset of stack-nodes V CXM are controlled by a first clock waveform and a second subset of stack-nodes V CXM are controlled by a second clock waveform;

(b) one or more stack-nodes V CXM in the first subset of stack-nodes V CXM are coupled to one respective first multiplexor, and the one respective first multiplexor is coupled to one corresponding first comparator circuit; and

(c) one or more stack-nodes V CXM in the second subset of stack-nodes V CXM are coupled to one respective second multiplexor, and the one respective second multiplexor is coupled to one corresponding second comparator circuit.

12. The invention of claim 1 , wherein all stack-nodes V CXM are coupled to a multiplexor comprising a matrix switch having a plurality of outputs, and one or more of the plurality of outputs is coupled to a respective one of n comparator circuits, where M×(N−1)>n≥1.

13. A method for measuring voltages in a power converter circuit comprising at least one set of N series switches where N≥2, each set configured as one of M charge pump legs where M≥1, wherein each pair of adjacent series switches in each charge pump leg defines a stack-node V CXM located between the adjacent series switches, where N−1≥X>1, the method including:

(a) performing a sequence of steps, including:

(1) selecting done stack-node V CXM by means of a multiplexor as an input to a comparator;

(2) applying a reference signal V REF as an input to the comparator;

(4) comparing the applied reference signal V REF to a proportional voltage representative of a voltage at the selected one stack-node V CXM ;

(5) outputting a signal indicative of the comparison; and

(b) repeating the sequence of steps for at least one other stack-node V CXM .

14. A method for testing pump capacitors in a charge pump by measuring voltages in a power converter circuit comprising at least one set of N series switches where N≥2, each set configured as one of M charge pump legs where M≥1, wherein each pair of adjacent series switches in each charge pump leg defines an associated stack-node V CXM located between the adjacent series switches, where N−1≥X>1, the method including:

(a) selecting a stack-node V CXM by means of a multiplexor as an input to a comparator;

(b) applying a reference signal V REF as an input to the comparator;

(c) comparing at a selected time the applied reference signal V REF to a proportional voltage representative of a voltage at the selected stack-node V CXM ;

(d) outputting a signal indicative of the comparison; and

(e) determining if the signal indicative of the comparison indicates that the selected stack-node V CXM meets an out-of-bound condition, and if so, asserting an error signal.

15. The method of claim 13 , further including adjusting the applied reference signal V REF for the selected stack-node V CXM before comparing the applied reference signal V REF to a voltage representative of a voltage at the selected stack-node V CXM .

16. The method of claim 14 , further including adjusting the applied reference signal V REF for the selected stack-node V CXM before comparing at a selected time the applied reference signal V REF to a voltage representative of a voltage at the selected stack-node V CXM .