Read-once memory

1. A memory, comprising:

a rewritable non-volatile flash memory cell;

input circuitry coupled to the memory cell, wherein the input circuitry, in operation, erases the memory cell in response to reception of a request to read the memory cell; and

output logic circuitry coupled to the memory cell, which, in operation, logically combines an indication of a read request and the output of the memory cell to generate an output response of the memory to the request to read the memory cell, wherein the input circuitry, in operation, erases the memory cell by programming the memory cell to a determined state before the output logic circuitry of the memory provides an output in response to the read request.

2. The memory of claim 1 , comprising a flip-flop having a set input coupled to an output of the memory cell.

3. The memory of claim 2 wherein the output logic circuitry, in operation, logically combines an output of the flip-flop and the output of the memory cell to generate the output response of the memory to the request to read the memory cell.

4. The memory of claim 3 , wherein the output logic circuitry includes an AND gate having an input which, in operation, receives an inverted output of the memory cell.

5. The memory of claim 2 , wherein the flip-flop is of RS type.

6. The memory of claim 1 wherein the output circuitry, in operation, sets the output response to a determined value after a reading of the memory cell.

7. The circuit of claim 1 , wherein the memory cell is of the type which is blank in a high state.

8. The circuit of claim 1 , wherein the memory cell and the input circuitry have a common clock.

9. The circuit of claim 2 , wherein the memory cell, the input circuitry and the flip-flop have a common clock.

10. A read-once memory, comprising:

an addressable, non-volatile flash memory having a plurality of rewriteable memory cells;

input circuitry coupled to the non-volatile memory, wherein the input circuitry, in operation, responds to reception of a request to read content stored at an address in the non-volatile memory by erasing the content stored at the address of the non-volatile memory; and

output circuitry coupled between the non-volatile memory and the output of the read-once memory, wherein the input circuitry, in operation, generates an output control signal, and the output circuitry, in operation, logically combines respective output bits of the non-volatile memory with the output control signal to generate a signal provided at the output of the read-once memory, wherein, in operation, the input circuitry erases the content stored at the address of the non-volatile memory cell before the output circuitry generates the signal provided at the output of the read-once memory.

11. The read-once memory of claim 10 wherein the output circuitry comprises one or more flip-flops coupled to respective output bits of the non-volatile memory.

12. The read-once memory of claim 11 wherein the output circuitry, in operation, logically combines outputs of the one or more flip-flops with the respective output bits of the non-volatile memory and the output control signal to generate a signal provided at the output of the read-once memory.

13. The read-once memory of claim 12 wherein the output circuitry comprises one or more AND gates, which, in operation, logically combine respective outputs of the one or more flip-flips with respective inverted output bits of the non-volatile memory and the output control signal to generate the signal provided at the output of the read-once memory.

14. The read-once memory of claim 12 wherein the flip-flop is an RS flip-flop.

15. The read-once memory of claim 12 wherein the output circuitry, in operation, sets the signal provided at the output of the read-once memory to a determined value after providing a response to a request to read content stored at the address in the non-volatile memory.

16. The read-once memory of claim 10 wherein the input circuitry, in operation, erases the memory cell by programming the memory cell to a determined state.

17. The read-once memory of claim 10 wherein the non-volatile memory, the input circuitry and the output circuitry have a common clock.

18. A system, comprising:

processing circuitry; and

a plurality of memories coupled to the processing circuitry, the plurality of memories including a read-once memory having:

an addressable, non-volatile flash memory with a plurality of rewriteable memory cells;

input circuitry coupled to the non-volatile memory, wherein the input circuitry, in operation, responds to reception of a request to read content stored at an address in the non-volatile memory by erasing the content stored at the address of the non-volatile memory and setting an output control signal to indicate a read request; and

output circuitry coupled between the non-volatile memory and an output of the read-once memory, wherein the output circuitry, in operation, logically combines an output of the non-volatile memory with the output control signal to generate a signal provided at the output of the read-once memory, wherein, in operation, the input circuitry erases the content stored at the address of the non-volatile memory before the output circuitry generates the signal provided at the output of the read-once memory.

19. The system of claim 18 wherein the output circuitry of the read-once memory comprises one or more flip-flops coupled to respective output bits of the non-volatile memory.

20. The system of claim 19 wherein the output circuitry of the read-once memory, in operation, logically combines outputs of the one or more flip-flops with the respective output bits of the non-volatile memory and the output control signal to generate a signal provided at the output of the read-once memory.

21. The system of claim 18 wherein the output circuitry, in operation, sets the signal provided at the output of the read-once memory to a determined state after providing a response to the request to read content stored at the address in the non-volatile memory.

22. A method, comprising:

storing content at an address of a read-once flash memory having a plurality of rewriteable memory cells; and

responding to reception of a request to read content stored at an address in the read-once memory by:

generating a control signal indicative of a read request;

erasing the content stored at the address of the read-once memory; and

providing the content in response to the request at an output of the read-once memory, wherein providing the content in response to the request comprises logically combining the content stored at the address of the read-once memory with the control signal indicative of the read request, wherein the content stored at the address of the read-once memory is erased before the content is provided in response to the request at the output of the read-once memory.

23. The method of claim 22 wherein providing the content in response to the request comprises logically combining respective output bits of the non-volatile memory with the control signal.