Electronic device forming a digital-to-analog converter and a mixer

1. A device, comprising:

an acquisition stage configured to receive a digital input signal and to generate, respectively, a first digital signal and a second digital signal, wherein the second digital signal is a logical inversion of the first digital signal;

a first processing stage and a second processing stage that are configured to receive, respectively, the first digital signal and the second digital signal, the first processing stage configured to generate a first analog signal in time with a first clock signal from the first digital signal, and the second processing stage configured to generate a second analog signal in time with a second clock signal from the second digital signal, wherein the second clock signal is phase opposite of the first clock signal; and

an output stage configured to generate an analog output signal equal to a selected one of the first analog signal or the second analog signal depending on the value of the first or second clock signal.

2. The device according to claim 1 , wherein the digital input signal and the first and second digital signals each include N bits, and the acquisition stage comprises N logic inverter circuits that are configured to generate, respectively, N bits of the second digital signal from N bits of the digital input signal.

3. The device according to claim 1 , wherein the first and second processing stages each include a digital-to-analog converter.

4. The device according to claim 3 , wherein each digital-to-analog converter of the first and second processing stages is a current-steering digital-to-analog converter.

5. The device according to claim 1 , wherein the first and second processing stages are identical.

6. The device according to claim 1 , wherein the output stage comprises an analog multiplexer configured to generate the analog output signal as equal to the first analog signal in response to a first logic state of the first or second clock signal or equal to the second analog signal in response to a second logic state of the first or second clock signal.

7. The device according to claim 6 , wherein the analog output signal has a phase shift corresponding to at least to the duration of a transient state of the first or second analog signal in a period of the first clock signal or the second clock signal.

8. The device according to claim 1 , produced in an integrated manner.

9. The device according to claim 1 , wherein the device comprises a communication system comprising an electronic device, the electronic device comprising the acquisition stage, the first processing stage, and the output stage.

10. The device according to claim 1 , wherein the device comprises a mobile phone including a communications system, the communications system comprising an electronic device, the electronic device comprising the acquisition stage, the first processing stage, and the output stage.

11. A device, comprising:

an acquisition stage configured to receive a digital input signal and generate a first digital signal and a second digital signal, wherein the second digital signal is a complement of the first digital signal;

a first digital to analog converter configured to convert the first digital signal to a first analog signal in time with a first clock signal;

a second digital to analog converter configured to convert the second digital signal to a second analog signal in time with a second clock signal;

wherein the second clock signal is a complement of the first clock signal; and

an output stage configured to:

generate an internal clock signal equivalent to one of: the first clock signal phase shifted by a duration of a transient state of the first clock signal that occurs during a period of the first clock signal, or the second clock signal phase shifted by a duration of a transient state of the second clock signal that occurs during a period of the second clock signal;

produce an analog output signal equal to the first analog signal when the internal clock signal is at a first logic level; and

produce the analog output signal equal to the second analog signal when the internal clock signal is at a second logic level opposite the first logic level.

12. The device of claim 11 , wherein the first and second digital to analog converters are each a current steering digital to analog converter.

13. The device according to claim 11 , wherein the digital input signal and the first and second digital signals each include N bits, and the acquisition stage comprises N inverter circuits configured to generate, respectively, N bits of the second digital signal from N bits of the digital input signal.

14. The device according to claim 11 , wherein the output stage comprises an analog multiplexer.

15. A method, comprising:

generating from a digital input signal a first digital signal and a second digital signal, wherein the second digital signal is a complement of the first digital signal;

converting the first digital signal to a first analog signal in time with a first clock signal;

converting the second digital signal to a second analog signal in time with a second clock signal, wherein the second clock signal is a complement of the first clock signal;

generating an internal clock signal equivalent to one of the first clock signal phase shifted by a duration of a transient state of the first clock signal that occurs during a period of the first clock signal, or the second clock signal phase shifted by a duration of a transient state of the second clock signal that occurs during a period of the second clock signal; and

producing an analog output signal by:

selecting the first analog signal as the analog output signal in response to a first logic state of the internal clock signal, and

selecting the second analog signal as the analog output signal in response to a second logic state of the internal clock signal.

16. The method of claim 15 , wherein the digital input signal and the first and second digital signals each include N bits.