IP Library Granted Patent US 11,025,169
Granted Patent B2
US 11,025,169 · App. 16/714,944 · Granted Jun 1, 2021

Overload protection for power converter

Inventors: Hyun-Chul Eum (Bucheon, KR); Young-Jong Kim (Seoul, KR)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H02M3/33507H02M1/08H02M1/32H02M3/33515H03G1/0088H05B45/00H05B45/10H05B45/37H05B45/395H05B45/44H05B45/48H05B45/50H02M2001/0009H02M2003/1566
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Quick Facts
Patent No.
US 11,025,169
App. No.
16/714,944
Granted
Jun 1, 2021
Kind
B2
Abstract

A circuit includes an overload monitor comparing a current sense signal to a threshold signal to generate a comparison result and adjusting a value of a first count signal in response to the comparison result and a monitoring signal. The monitoring signal indicates a time interval during which the overload monitor adjusts the value of the first count signal. The circuit further includes an overload protection signal generator generating an overload protection signal in response to the first count signal, the overload protection signal indicating whether the power converter is operating in an overload condition.

Claims (60)

1. A circuit for controlling a power converter, comprising:

an overload monitor configured to compare a current sense signal to a threshold signal to generate a first comparison result, and to adjust a value of a first count signal in response to the first comparison result and a monitoring signal, the monitoring signal indicating a time interval during which the overload monitor adjusts the value of the first count signal; and

an overload protection signal generator configured to generate an overload protection signal in response to the first count signal, the overload protection signal indicating whether the power converter is operating in an overload condition,

wherein the overload monitor further comprises:

a first comparator generating a first comparison signal indicative of the first comparison result of the current sense signal to the threshold signal; and

a first flip-flop receiving the first comparison signal and a modulation signal to generate a first output signal in response to the first comparison signal and the modulation signal, the modulation signal being applied to a switching device of the power converter.

2. The circuit of claim 1 , wherein the overload monitor includes a first counter circuit that increases the value of the first count signal when a value of the current sense signal is equal to or greater than a value of the threshold signal and the monitoring signal has a first logic value.

3. The circuit of claim 2 , wherein the overload monitor further includes a second counter circuit that adjusts a value of a second count signal when the value of the first count signal is equal to or greater than a value of a first reference signal and the monitoring signal has a second logic value.

4. The circuit of claim 2 ,

wherein the overload monitor further comprises:

a first logic gate generating a first intermediate output signal in response to the first output signal and an oscillation signal; and

a second logic gate generating a first counter input signal in response to the first intermediate output signal and the monitoring signal and outputting the first counter input signal to the first counter circuit.

5. The circuit of claim 4 , wherein the overload monitor further comprises:

a third logic gate generating a second intermediate output signal in response to an inverted version of the first output signal and the oscillation signal; and

a fourth logic gate generating a second counter input signal in response to the second intermediate output signal and the monitoring signal and outputting the second counter input signal to the first counter circuit.

6. The circuit of claim 4 , wherein the overload monitor further comprises:

a second comparator generating a second comparison signal indicative of a second comparison result of the first count signal to a first reference signal;

a second flip-flop generating a second output signal in response to the second comparison signal and the monitoring signal; and

a second counter circuit generating a second count signal in response to the second output signal.

7. The circuit of claim 1 ,

wherein the overload monitor is further configured to compare the first count signal to a first reference signal and to adjust a value of a second count signal in response to a second comparison result of the first count signal to the first reference signal.

8. The circuit of claim 7 , wherein the overload protection signal generator generates the overload protection signal that has a specific logic value when the value of the second count signal has a given value relative to that of a second reference signal, the specific logic value of the overload protection signal indicating that the power converter is operating in the overload condition.

9. The circuit of claim 1 , wherein an on-time duration of the monitoring signal is equal to or longer than 60%, 75%, 90%, 95%, 97%, or 99% of a cycle time of an input signal, the input signal being a rectified version of an AC signal received by the power converter.

10. A power converter, comprising:

a switching device; and

an overload protection circuit configured to determine whether the power converter is operating in an overload condition based on a current sense signal, the current sense signal indicating a magnitude of a current that flows through the switching device,

wherein the overload protection circuit includes:

an overload monitor configured to compare the current sense signal to a threshold signal to generate a comparison result, and to adjust a value of a first count signal in response to the comparison result and a monitoring signal, the monitoring signal indicating a time interval during which the overload monitor adjusts the value of the first count signal; and

an overload protection signal generator configured to generate an overload protection signal in response to the first count signal, the overload protection signal indicating whether the power converter is operating in the overload condition, and

wherein the overload monitor includes:

a first counter circuit that increases the value of the first count signal when a value of the current sense signal is equal to or greater than a value of the threshold signal and the monitoring signal has a first logic value; and

a second counter circuit that receives the monitoring signal and increases a value of a second count signal when the value of the first count signal is equal to or greater than a value of a reference signal and the monitoring signal has transitions from the first logic value to a second logic value.

11. The power converter of claim 10 , wherein the first counter circuit receives the monitoring signal to reset the value of the first count signal when the monitoring signal transitions from the first logic value to the second logic value.

12. A method of controlling a power converter, the method comprising:

comparing a current sense signal to a threshold signal to generate a first comparison result;

adjusting a value of a first count signal in response to the first comparison result and a monitoring signal, the monitoring signal indicating a time interval during which the overload monitor adjusts the value of the first count signal;

generating a first comparison signal indicative of the first comparison result of the current sense signal to the threshold signal;

receiving the first comparison signal and a modulation signal to generate a first output signal in response to the first comparison signal and the modulation signal, the modulation signal being applied to a switching device of the power converter; and

generating an overload protection signal in response to the first count signal, the overload protection signal indicating whether the power converter is operating in an overload condition.

13. The method of claim 12 , further comprising:

increasing the value of the first count signal when a value of the current sense signal is equal to or greater than a value of the threshold signal and the monitoring signal has a first logic value.

14. The method of claim 13 , further comprising:

increasing a value of a second count signal when the value of the first count signal is equal to or greater than a value of a first reference signal and the monitoring signal has a second logic value.

15. The method of claim 13 , further comprising:

generating a first intermediate output signal in response to the first output signal and an oscillation signal; and

generating a first counter input signal in response to the first intermediate output signal and the monitoring signal.

16. The method of claim 15 , further comprising:

generating a second intermediate output signal in response to an inverted version of the first output signal and the oscillation signal; and

generating a second counter input signal in response to the second intermediate output signal and the monitoring signal to provide the second counter input signal.

17. The method of claim 15 , further comprising:

generating a second comparison signal indicative of a second comparison result of the first count signal to a first reference signal;

generating a second output signal in response to the second comparison signal and the monitoring signal; and

generating a second count signal in response to the second output signal.

18. The method of claim 12 , further comprising:

comparing the first count signal to a first reference signal; and

adjusting a value of a second count signal in response to a second comparison result of the first count signal to the first reference signal.

19. The method of claim 18 , further comprising:

comparing the second count signal to a second reference signal; and

asserting the overload protection signal to a specific logic value when the value of the second count signal has a given value relative to that of the second reference signal.

20. The method of claim 12 , wherein the input signal is a rectified version of an AC signal received by the power converter.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 054090, FRAME 0617 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064081/0167 →
SECURITY INTEREST Recorded Oct 16, 2020
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION; ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 054090/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2019
From: EUM, HYUN-CHUL; KIM, YOUNG-JONG
To: FAIRCHILD KOREA SEMICONDUCTOR LTD.
Reel/Frame 051289/0549 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2019
From: FAIRCHILD KOREA SEMICONDUCTOR LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 051302/0235 →