Methods and systems relating to ultra wideband broadcasting
Within many applications impulse radio based ultra-wideband (IR-UWB) transmission offers significant benefits for very short range high data rate communications when compared with existing standards and protocols. In many of these applications the main design goals are very low power consumption and very low complexity design for easy integration and cost reduction. Digitally programmable IR-UWB transmitters using an on-off keying modulation scheme on a 0.13 microns CMOS process operating on 1.2V supply and yielding power consumption as low as 0.9 mW at a 10 Mbps data rate with dynamic power control are enabled. The IR-UWB transmitters support new frequency hopping techniques providing more efficient spectrum usage and dynamic allocation of the spectrum when transmitting in highly congested frequency bands. Biphasic scrambling is also introduced for spectral line reduction. Additionally, an energy detection receiver for IR-UWB is presented to similarly meet these design goals whilst being adaptable to address IR-UWB transmitter specificity.
1. A method of receiving data comprising:
receiving a plurality of wireless pulse sequences with a wireless receiver;
establishing a configuration of a receiver circuit with a control circuit forming part of the receiver; and
processing the plurality of wireless pulse sequences with a receiver circuit to generate a plurality of bits of data; wherein
the receiver circuit generates a bit of the plurality of bits of data from each wireless pulse sequence of the plurality of wireless pulse sequences;
the receiver circuit incorporates an integrator integrating over an integration window established in dependence upon a template waveform;
each pulse sequence of the plurality of wireless pulse sequences has a predetermined duration within which are a plurality N pulses with each pulse of the plurality of N pulses having a predetermined frequency of a plurality M frequencies, a predetermined amplitude, and a predetermined pulse length, wherein M and N are integers;
the control circuit includes a power cycling controller comprising a plurality of non-overlapping signal generation circuits and employs the template waveform to determine when to power up or power down different predetermined portions of the receiver circuit;
each non-overlapping signal generation circuit of the plurality of non-overlapping signal generation circuits is coupled to one of the different predetermined portions of the receiver circuit and generates control signals to power up or power down that predetermined portion of the receiver circuit; and
the plurality of non-overlapping signal generation circuits and integration window of the integrator are aligned through being generated from the same template waveform.
2. The method according to claim 1 , further comprising
establishing the configuration of the receiver circuit in dependence upon receipt of a training sequence prior to receipt of the plurality of wireless pulse sequences.
3. The method according to claim 1 , further comprising
establishing the configuration of the receiver circuit in dependence upon receipt of a training sequence prior to receipt of the plurality of wireless pulse sequences;
wherein
the receiver circuit comprises the integrator having a plurality of outputs wherein the control circuit establishes a reference level in dependence upon the plurality of outputs such that the receiver circuit is configured to offset at least one of a baseline noise power of the receiver circuit and background noise in a transmission channel from a transmitter to a receiver comprising the receiver circuit.
4. The method according to claim 1 , wherein
the plurality of non-overlapping signal generation circuits are timed to reduce impact on the receiver circuit generate the plurality of bits whilst reducing power consumption of the receiver circuit.
5. The method according to claim 1 , wherein
the receiver circuit having at least one power down recovery circuit including a biasing resistor coupled in parallel with an NMOS transistor which is coupled to the control signal associated with the predetermined portion of the receiver circuit such that when the control signal is active the parallel NMOS transistor provides a low impedance path to a voltage source coupled to the biasing resistor.
6. The method according to claim 1 , wherein
the receiving circuit comprises the integrating circuit employing a transconductance amplifier with feedback via a feedback resistance and a feedback capacitance value and a reset transistor;
the feedback capacitance value being changed between two settings in dependence upon a first control signal from the control circuit coupled to transistor shorting a first capacitor and leaving a second capacitor allowing the integrating circuit to have two sensitivity settings;
the reset transistor in dependence upon a second control signal from the control circuit allows an input and output of the integrating circuit to be shorted together providing control of the integration window where the reset transistor is open only during integration of each wireless pulse sequence of the plurality of wireless pulse sequences and closed when no wireless pulse bundle sequence of the plurality of wireless pulse sequences is expected.
7. The method according to claim 1 , wherein
the receiving circuit comprises an energy detector which multiplies a wireless pulse sequence of the plurality of wireless pulse sequences with itself by coupling a differential signal generated in dependence upon the wireless pulse sequence of the plurality of wireless pulse sequences to a balanced mixer.
8. The method according to claim 7 , wherein
the receiver circuit is synchronized with a transmitter generating the plurality of wireless pulse sequences by processing a training sequence transmitted by the transmitter prior to transmitting the plurality of wireless pulse sequences.
9. A receiver for receiving data comprising:
an antenna for receiving a plurality of wireless pulse sequences;
a receiver circuit coupled to the antenna for processing the plurality of wireless pulse sequences to generate a plurality of bits of data; and
a control circuit for establishing a configuration of the receiver circuit; wherein
the receiver circuit generates a bit of the plurality of bits of data from each wireless pulse of the plurality of wireless pulses;
the receiver circuit incorporates an integrator integrating over an integration window established in dependence upon a template waveform;
each wireless pulse sequence of the plurality of wireless pulse sequences has a predetermined duration within which are a plurality N pulses with each pulse of the plurality of N pulses having a predetermined frequency of a plurality M frequencies, a predetermined amplitude, and a predetermined pulse length, wherein M and N are integers;
the control circuit includes a power cycling controller comprising a plurality of non-overlapping signal generation circuits and employs the template waveform to determine when to power up or power down different predetermined portions of the receiver circuit;
each non-overlapping signal generation circuit of the plurality of non-overlapping signal generation circuits is coupled to a different predetermined portion of the receiver circuit and generates control signals to power up or power down that predetermined portion of the receiver circuit; and
the plurality of non-overlapping signal generation circuits and integration window of the integrator are aligned through being generated from the same template waveform.
10. The receiver according to claim 9 , wherein
the configuration of the receiver circuit is established in dependence upon receipt of a training sequence prior to receipt of the plurality of wireless pulse sequences.
11. The receiver according to claim 9 , further comprising
the configuration of the receiver circuit is established in dependence upon receipt of a training sequence prior to receipt of the plurality of wireless pulse sequences;
wherein
the receiver circuit comprises the integrator having a plurality of outputs wherein the control circuit establishes a reference level in dependence upon the plurality of outputs such that the receiver circuit is configured to offset at least one of a baseline noise power of the receiver circuit and background noise in a transmission channel from a transmitter to a receiver comprising the receiver circuit.
12. The receiver according to claim 9 , wherein
the plurality of non-overlapping signal generation circuits are timed to reduce impact on the receiver circuit generate the plurality of bits whilst reducing power consumption of the receiver circuit.
13. The receiver according to claim 9 , wherein
the receiver circuit having at least one power down recovery circuit including a biasing resistor coupled in parallel with an NMOS transistor which is coupled to the control signal associated with the predetermined portion of the receiver circuit such that when the control signal is active the parallel NMOS transistor provides a low impedance path to a voltage source coupled to the biasing resistor.
14. The receiver according to claim 9 , wherein
the receiving circuit comprises the integrating circuit employing a transconductance amplifier with feedback via a feedback resistance and a feedback capacitance value and a reset transistor;
the feedback capacitance value being changed between two settings in dependence upon a first control signal from the control circuit coupled to transistor shorting a first capacitor and leaving just a second capacitor allowing the integrating circuit to have two sensitivity settings;
the reset transistor in dependence upon a second control signal from the control circuit allows an input and output of the integrating circuit to be shorted together providing control of the integration window where the reset transistor is open only during integration of each wireless pulse sequence of the plurality of wireless pulse sequences and closed when no wireless pulse sequence of the plurality of wireless pulse sequences is expected.
15. The receiver according to claim 9 , wherein
the receiving circuit comprises an energy detector which multiplies a wireless pulse sequence of the plurality of wireless pulse sequences with itself by coupling a differential signal generated in dependence upon the wireless pulse sequence of the plurality of wireless pulse sequences to a balanced mixer.
16. The receiver according to claim 7 , wherein
the receiver circuit is synchronized with a transmitter generating the plurality of wireless pulse sequences by processing a training sequence transmitted by the transmitter prior to transmitting the plurality of wireless pulse sequences.
17. A method of receiving data comprising:
receiving a plurality of wireless pulse sequences with a wireless receiver; establishing a configuration of a receiver circuit with a control circuit forming part of the receiver; and
processing the plurality of wireless pulse sequences with a receiver circuit to generate a plurality of bits of data; wherein
the receiver circuit generates a bit of the plurality of bits of data from each wireless pulse sequence of the plurality of wireless pulse sequences;
the receiving circuit comprises an integrating circuit employing a transconductance amplifier with feedback via a feedback resistance and a feedback capacitance value and a reset transistor;
the feedback capacitance value being changed between two settings in dependence upon a first control signal from the control circuit coupled to transistor shorting a first capacitor and leaving just a second capacitor allowing the integrating circuit to have two sensitivity settings;
the reset transistor in dependence upon a second control signal from the control circuit allows an input and output of the integrating circuit to be shorted together providing control of the integration window where the reset transistor is open only during integration of each wireless pulse sequence of the plurality of wireless pulse sequences and closed when no wireless pulse sequence of the plurality of wireless pulse sequences is expected;
each pulse sequence of the plurality of wireless pulse sequences has a predetermined duration within which are a plurality N pulses with each pulse of the plurality of N pulses having a predetermined frequency of a plurality M frequencies, a predetermined amplitude, and a predetermined pulse length, wherein M and N are integers.
18. A receiver for receiving data comprising:
an antenna for receiving a plurality of wireless pulse sequences;
a receiver circuit coupled to the antenna for processing the plurality of wireless pulse sequences to generate a plurality of bits of data; and
a control circuit for establishing a configuration of the receiver circuit; wherein
the receiver circuit generates a bit of the plurality of bits of data from each wireless pulse sequence of the plurality of wireless pulse sequences;
the receiving circuit comprises an integrating circuit employing a transconductance amplifier with feedback via a feedback resistance and a feedback capacitance value and a reset transistor;
the feedback capacitance value being changed between two settings in dependence upon a first control signal from the control circuit coupled to transistor shorting a first capacitor and leaving just a second capacitor allowing the integrating circuit to have two sensitivity settings;
the reset transistor in dependence upon a second control signal from the control circuit allows an input and output of the integrating circuit to be shorted together providing control of the integration window where the reset transistor is open only during integration of each wireless pulse sequence of the plurality of wireless pulse sequences and closed when no wireless pulse sequence of the plurality of wireless pulse sequences is expected;
each pulse sequence of the plurality of wireless pulse sequences has a predetermined duration within which are a plurality N pulses with each pulse of the plurality of N pulses having a predetermined frequency of a plurality M frequencies, a predetermined amplitude, and a predetermined pulse length, wherein M and N are integers.