IP Library Granted Patent US 11,245,774
Granted Patent B2
US 11,245,774 · App. 16/715,717 · Granted Feb 8, 2022

Cache storage for streaming data

Inventor: Andrei Paduroiu (Bellevue, WA)
Assignee: EMC IP Holding Company LLC
H04L67/2842G06F12/0891G06F12/1045H04L43/0882H04L65/60H04L67/1097G06F12/0871G06F12/0888G06F2212/1024G06F2212/154
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Quick Facts
Patent No.
US 11,245,774
App. No.
16/715,717
Granted
Feb 8, 2022
Kind
B2
Abstract

Described herein are systems and techniques to efficiently cache data for streaming applications. A cache can be organized to include multiple cache segments, and each cache segment can include multiple cache blocks. A cache entry can be created for streaming data, and the streaming data can be streamed directly into a first cache block. When the first cache block is full, a next cache block can be identified, in a same cache segment or in a new cache segment. The streaming data can be streamed directly into the next cache block, and into any further cache blocks as needed.

Claims (37)

1. A method, comprising:

identifying, by a device comprising a processor, a first cache block in a first cache segment of multiple cache segments of a cache storage, wherein each respective cache segment of the multiple cache segments comprises a respective metadata block and multiple respective cache blocks;

storing, by the device, in the first cache block, a first portion of a cache entry comprising a first portion of a data stream;

in response to an indication that the first cache block is full, identifying, by the device, a second cache block in the cache storage;

storing, by the device, in the second cache block, a second portion of the cache entry comprising a second portion of the data stream; and

storing, by the device, a pointer in the respective metadata block within the respective cache segment comprising the second cache block, wherein the pointer points to the first cache block.

2. The method of claim 1 , wherein the multiple cache segments are equal sized and wherein the multiple respective cache blocks are equal sized.

3. The method of claim 1 , wherein the respective metadata block within the respective cache segment comprising the second cache block comprises the pointer and an indication that the second cache block is allocated to the cache entry.

4. The method of claim 1 , wherein identifying the first cache block in the cache storage comprises checking a cache index for a last used cache block identification, and wherein the method further comprises updating, by the device, the last used cache block identification in the cache index to identify a final cache block comprising a final portion of the cache entry.

5. The method of claim 1 , further comprising, in response to an indication that the first cache segment is full, identifying, by the device, a second cache segment in the cache storage, and wherein the second cache block is in the second cache segment.

6. The method of claim 1 , further comprising performing, by the device, a cache cleanup in response to an indication that the cache storage is full.

7. The method of claim 1 , further comprising outputting, by the device, a cache utilization measurement indicating a proportion of the cache storage which is in use.

8. The method of claim 1 , further comprising, in response to the cache entry reaching a size limit, creating, by the device, an additional cache entry to store an additional portion of the data stream.

9. The method of claim 1 , further comprising storing, by the device, cache entry index data comprising cache entries and corresponding cache blocks.

10. A device, comprising:

at least one processor; and

at least one memory that stores executable instructions that, when executed by the at least one processor, facilitate performance of operations, comprising:

storing a data stream in a cache storage comprising multiple equal sized cache segments, each cache segment comprising a respective metadata block and multiple equal sized cache blocks,

wherein the data stream is stored as a cache entry in at least one cache block, the at least one cache block comprising a last used cache block in the cache storage;

storing cache entry index data comprising:

a cache entry identifier for the cache entry; and

a first cache segment identifier and a first cache block identifier for the at least one cache block; and

reading the cache entry by referencing the cache entry identifier in the cache entry index data, and reading data from the at least one cache block identified by the cache segment identifier and a cache block identifier.

11. The device of claim 10 , wherein the at least one cache block further comprises at least one additional cache block in the cache storage, in addition to the last used cache block in the cache storage.

12. The device of claim 11 , wherein the operations further comprise identifying a free cache block in a cache segment comprising the last used cache block, and using the free cache block as the at least one additional cache block.

13. The device of claim 11 , wherein the operations further comprise, in response to identifying no free cache blocks in a cache segment comprising the last used cache block, identifying an additional cache segment comprising a free cache block, and using the free cache block as the at least one additional cache block.

14. The device of claim 11 , wherein the operations further comprise storing a pointer in the respective metadata block for a cache segment comprising the at least one additional cache block, and wherein the pointer points to a previous cache block comprising a previous portion of the cache entry.

15. The device of claim 11 , wherein the cache entry index data further comprises a final cache segment identifier and a final cache block identifier for a final cache block of the at least one additional cache block.

16. A non-transitory machine-readable medium, comprising executable instructions that, when executed by a processor, facilitate performance of operations, comprising:

directing a data stream to a cache storage, the cache storage comprising multiple cache segments, each cache segment comprising a respective metadata block and multiple cache blocks;

storing the data stream in the multiple cache blocks of the cache storage by serially filling free cache blocks with the data stream;

in response to identifying a next free cache block for use in the serially filling of the free cache blocks with the data stream, reporting a cache utilization measurement indicating a proportion of the cache storage which is in use; and

throttling a rate at which the data stream is directed to the cache storage as a function of the cache utilization measurement.

17. The non-transitory machine-readable medium of claim 16 , wherein the throttling the rate at which the data stream is directed to the cache storage as a function of the cache utilization measurement comprises setting a throttling delay when the cache utilization measurement is above a throttling threshold.

18. The non-transitory machine-readable medium of claim 16 , wherein the operations further comprise evicting one or more previous data streams from the cache storage in response to the cache utilization measurement exceeding an eviction threshold.

19. The non-transitory machine-readable medium of claim 16 , wherein the data stream is stored as at least one cache entry in the multiple cache blocks of the cache storage.

20. The non-transitory machine-readable medium of claim 16 , wherein the storing the data stream in the multiple cache blocks of the cache storage by the serially filling of the free cache blocks with the data stream comprises serially filling of the free cache blocks of each respective cache segment of the multiple cache segments.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053311/0169) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
Reel/Frame 060438/0742 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (052216/0758) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 060438/0680 →
RELEASE OF SECURITY INTEREST AF REEL 052243 FRAME 0773 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058001/0152 →
SECURITY INTEREST Recorded Jun 5, 2020
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 053311/0169 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 26, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 052243/0773 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Mar 24, 2020
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 052216/0758 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2019
From: PADUROIU, ANDREI
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 051295/0937 →