IP Library Granted Patent US 10,997,915
Granted Patent B2
US 10,997,915 · App. 16/717,277 · Granted May 4, 2021

Pixel circuit, method for driving, and display device

Inventor: Masanori Ohara (Tokyo, JP)
Assignee: JOLED INC.
G09G3/3233G09G3/2074G09G3/3283G09G2300/0842G09G2310/08G09G2320/0242
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Quick Facts
Patent No.
US 10,997,915
App. No.
16/717,277
Granted
May 4, 2021
Kind
B2
Abstract

A pixel circuit includes: one data signal line; one holding capacitor which holds a data signal transmitted through the one data signal line; one drive transistor which outputs a current in accordance with the data signal held at the one holding capacitor; three color selection lines; three color selection transistors having control terminals respectively connected to the three color selection lines that are mutually different; and three light emitting elements being connected to an output end of the current of the one drive transistor via the three color selection transistors, respectively, that are mutually different, and emitting luminescent colors that are mutually different.

Claims (51)

1. A pixel circuit, comprising:

one data signal line;

one holding capacitor which holds a data signal transmitted through the one data signal line;

one drive transistor which outputs a current in accordance with the data signal held at the one holding capacitor;

three color selection lines;

three color selection transistors having control terminals respectively connected to the three color selection lines, the three color selection transistors being mutually different; and

three light emitting elements connected to an output end, which outputs the current, of the one drive transistor via the three color selection transistors, respectively, the three light emitting elements being mutually different and emitting luminescent colors that are mutually different,

wherein the pixel circuit is arranged in a pixel region, the pixel region including three sub-pixel regions, the three sub-pixel regions being mutually different,

the three light emitting elements are respectively arranged in the three sub-pixel regions, and

the three color selection transistors are arranged in one of three sub-pixel regions in which the one drive transistor is arranged.

2. A display device, comprising:

a plurality of pixel circuits each being the pixel circuit according to claim 1 , the plurality of pixel circuits being arranged in a matrix,

wherein the one data signal line provided in each of the plurality of pixel circuits arranged in each column of the matrix is connected together,

the three color selection lines provided for the luminescent colors in each of the plurality of pixel circuits arranged in each row of the matrix and corresponding to a same luminescent color are respectively connected together, and

the display device further comprises:

a data driver connected to the one data signal line in each column; and

a gate driver connected to the three color selection lines in each row.

3. The display device according to claim 2 , further comprising:

a timing controller, wherein

under control of the timing controller in each subframe period of three subframe periods, the three subframe periods forming one frame period and respectively corresponding to the luminescent colors that are mutually different:

the data driver supplies, to the one data signal line in each column, a data signal related to light emission luminance of one of the luminescent colors corresponding to the subframe period, and

the gate driver supplies, sequentially row by row to one of the three color selection lines for the one of the luminescent colors corresponding to the subframe period in each row, a control signal for controlling, into a conductive state, one of the three color selection transistors connected to a corresponding one of the three color selection lines for the one of the luminescent colors corresponding to the subframe period in each row.

4. The pixel circuit according to claim 1 , wherein

the one holding capacitor is arranged in the one of the three sub-pixel regions, and

the one data signal line is arranged in any of the three sub-pixel regions other than the one of the three sub-pixel regions.

5. The pixel circuit according to claim 1 , further comprising:

one first reference voltage line; and

a compensation transistor connected between the one first reference voltage line and a gate node of the one drive transistor,

wherein the one first reference voltage line is arranged only in a second one of the three sub-pixel regions in which the one drive transistor is not arranged.

6. The pixel circuit according to claim 1 , further comprising:

one second reference voltage line; and

an initialization transistor connected between the one second reference voltage line and a source node of the one drive transistor,

wherein the one second reference voltage line is arranged only in a second one of the three sub-pixel regions in which the one drive transistor is not arranged.

7. A method for driving a pixel circuit including one data signal line, one holding capacitor, one drive transistor, three color selection transistors, and three light emitting elements, the method comprising:

in each subframe period of three subframe periods, the three subframe periods forming one frame period and respectively corresponding to luminescent colors, the luminescent colors being mutually different:

holding a data signal at the one holding capacitor via the one data signal line, the data signal being related to light emission luminance of one of the luminescent colors corresponding to the subframe period;

outputting, from the one drive transistor, a current in accordance with the data signal held at the one holding capacitor; and

supplying, via one of the three color selection transistors, the current outputted from the one drive transistor to a corresponding one of the three light emitting elements that emits the one of the luminescent colors corresponding to the subframe period,

wherein the pixel circuit is arranged in a pixel region, the pixel region including three sub-pixel regions, the three sub-pixel regions being mutually different,

the three light emitting elements are respectively arranged in the three sub-pixel regions, and

the three color selection transistors are arranged in one of three sub-pixel regions in which the one drive transistor is arranged.

8. The method according to claim 7 , wherein

the pixel circuit further includes:

one first reference voltage line; and

a compensation transistor connected between the one first reference voltage line and a gate node of the one drive transistor, and

the one first reference voltage line is arranged only in a second one of the three sub-pixel regions in which the one drive transistor is not arranged.

9. The method according to claim 7 , wherein

the pixel circuit further includes:

one second reference voltage line; and

an initialization transistor connected between the one second reference voltage line and a source node of the one drive transistor, and

the one second reference voltage line is arranged only in a second one of the three sub-pixel regions in which the one drive transistor is not arranged.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2019
From: OHARA, MASANORI
To: JOLED INC.
Reel/Frame 051309/0270 →