Enhanced input of machine-learning accelerator activations

1. A processor comprising:

a plurality of tiles;

a plurality of activation lines that couple a memory device to a respective tile, wherein the memory device is configured to store an array of input data;

a plurality of delay registers that are each paired with a respective activation line; and

scheduling circuitry that is configured to select a respective input activation for each tile of the plurality of tiles from either an activation line for the tile or a delay register for the activation line, the delay register holding data previously carried by the activation line,

wherein each tile, upon receiving an input activation from an activation line or a delay register, is configured to multiply the input activation by a respective weight of a plurality of weights of a kernel to generate a partial sum of a particular operation.

2. The processor of claim 1 , wherein the processor is a machine-learning accelerator.

3. The processor of claim 1 , wherein the particular operation is a convolution operation, and wherein the plurality of weights are a plurality of weights of a convolution kernel.

4. The processor of claim 1 , further comprising a vector accumulator that is configured to compute an accumulated sum from partial sums computed by each of the plurality of tiles.

5. The processor of claim 1 , wherein the processor is configured to read new values from the memory device on each of a plurality of global ticks.

6. The processor of claim 5 , wherein the scheduling circuitry is configured to select input activations in a pattern in which a number of delay registers used decreases on each local tick of each global tick and a number of activation lines used increases on each local tick of each global tick.

7. The processor of claim 6 , wherein the scheduling circuitry is configured to compute an output value using data from three delay registers and no activation lines for each row group of a plurality of row groups in the array of input data on a first local tick, compute an output value using data from two delay registers and one activation line for each row group on a second local tick, and compute an output value using data from one delay register and two activation lines for each row group on a third local tick.

8. The processor of claim 1 , wherein each input activation is read from the memory device only once per row group.

9. The processor of claim 1 , wherein the processor is configured to overwrite data in the delay registers with data from a paired activation line on each global tick.

10. A method performed by a processor comprising:

a plurality of tiles;

a plurality of activation lines that couple a memory device to a respective tile, wherein the memory device stores an array of input data;

a plurality of delay registers that are each paired with a respective activation line; and

scheduling circuitry,

the method comprising:

selecting, by the scheduling circuitry, a respective input activation for each tile of the plurality of tiles from either an activation line for the tile or a delay register for the activation line, the delay register holding data previously carried by the activation line, and

upon receiving, by each tile, an input activation from an activation line or a delay register, multiplying, by the tile, the input activation by a respective weight of a plurality of weights of a kernel to generate a partial sum of a particular operation.

11. The method of claim 10 , wherein the processor is a machine-learning accelerator.

12. The method of claim 10 , wherein the particular operation is a convolution operation, and wherein the plurality of weights are a plurality of weights of a convolution kernel.

13. The method of claim 10 , further comprising computing, by a vector accumulator, an accumulated sum from partial sums computed by each of the plurality of tiles.

14. The method of claim 10 , further comprising reading new values from the memory device on each of a plurality of global ticks.

15. The method of claim 14 , further comprising selecting, by the scheduling logic, input activations in a pattern in which a number of delay registers used decreases on each local tick of each global tick and a number of activation lines used increases on each local tick of each global tick.

16. The method of claim 15 , further comprising computing an output value using data from three delay registers and no activation lines for each row group of a plurality of row groups in the array of input data on a first local tick, compute an output value using data from two delay registers and one activation line for each row group on a second local tick, and compute an output value using data from one delay register and two activation lines for each row group on a third local tick.

17. The method of claim 10 , wherein each input activation is read from the memory device only once per row group.

18. The method of claim 10 , further comprising overwriting data in the delay registers with data from a paired activation line on each global tick.