Hardware sort accelerator sharing first level processor cache

1. A computer system configured to sort data, the computer system comprising:

a processor cache in signal communication with a separate memory unit installed in the computer system, and configured to determine a plurality of key values stored in the separate memory unit;

a hardware merge sort accelerator in signal communication with the separate memory unit and the processor cache, the merge sort accelerator configured to generate a tournament tree based on the key values obtained from the processor cache, and to perform a partial tournament sort to determine an overall winning key value among a list of key values participating in the partial tournament sort; and

a main memory unit including memory locations configured to store each overall winning key value,

wherein the main memory unit is continuously updated in response to storing the overall winning key such that each overall winning key is automatically stored sequentially with respect to one another.

2. The computer system of claim 1 , wherein each key value represents a numeral including a plurality of digits.

3. The computer system of claim 2 , wherein the merge sort accelerator executes the partial tournament sort by performing a first tournament to determine a first overall winning digit of the overall winning key value, and performing a second tournament to determine winner of a second overall winning digit of the overall winning key value.

4. The computer system of claim 1 , wherein the merge sort accelerator configured to generate a tournament tree based on the key values and perform a partial tournament sort to store a first portion of tournament results in the processor cache while excluding a second portion of the tournament results from the processor cache.

5. The computer processor of claim 1 , wherein the merge sort accelerator determines the first portion of the tournament results based on a winning digit of a given match between a first digit of a first key value and a first digit of a second key value different from the first key value.

6. The computer processor of claim 5 , wherein the merge sort accelerator determines the winning digit as a lowest value among a comparison between digits of the first and second keys of the given match.

7. The computer processor of claim 5 , wherein the merge sort accelerator determines the overall winning key value of the partial tournament sort by selecting a key value from the tournament list and performing a plurality of passes through the tournament tree using the selected key value.

8. The computer processor of claim 7 , wherein the overall winning key value is stored from the merge sort accelerator to the main memory unit.

9. A computer-implemented method of updating a computer system with sequentially sorted data, the method comprising:

obtaining, via a processor cache, a plurality of key values stored in a memory unit installed on the computer system;

generating, via a hardware merge sort accelerator, a tournament tree based on the key values obtained from the processor cache;

determining, via the merge sort accelerator, a plurality of overall winning key value among a list of key values participating in a partial tournament sort; and

continuously updating the memory unit with the plurality of the overall winning key values that are automatically stored sequentially with respect to one another in response to storing a most recent determined overall winning key value in the memory unit.

10. The method of claim 9 , further comprising using each key value to represent a numeral having a plurality of digits.

11. The method of claim 10 , further comprising:

performing a first tournament to determine a first digit of an overall winning key value; and

performing a second tournament to determine a second digit of the overall winning key value.

12. The method of claim 9 , further comprising generating, via the merge sort accelerator, a tournament tree based on the key values.

13. The method of claim 12 , further comprising performing, via the merge sort accelerator, a partial tournament sort to store a first portion of tournament results in the processor cache while excluding a second portion of the tournament results from the processor cache.

14. The method of claim 9 , further comprising determining, via the merge sort accelerator, the first portion of the tournament results based on a winning digit of a given match between a first digit of a first key value and a first digit of a second key value different from the first key value.

15. The method of claim 14 , further comprising determining, via the merge sort accelerator, the winning digit as a lowest value among a comparison between digits of the first and second keys of the given match.

16. The method of claim 14 , further comprising determining, via the merge sort accelerator, the overall winning key value of the partial tournament sort by selecting a key value from the tournament list and performing a plurality of passes through the tournament tree using the selected key value.

17. The method of claim 16 , further comprising storing the overall winning key value from the merge sort accelerator to the memory unit.