Apparatus, systems, and methods for low power computational imaging
The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.
1. An electronic device, comprising:
a memory fabric including memory slices, the memory fabric structured to allow parallel access to (a) first ones of the memory slices corresponding to at least one vector processor and (b) second ones of the memory slices corresponding to at least one hardware accelerator;
a first data bus communicatively connected to the memory fabric, the first data bus to facilitate data transfer between the at least one vector processor and the first ones of the memory slices;
a second data bus communicatively connected to the memory fabric, the second data bus to facilitate data transfer between the at least one hardware accelerator and the second ones of the memory slices; and
a third data bus to facilitate data transfer between: (a) at least one peripheral device and the at least one vector processor, and (b) the at least one vector processor and the at least one hardware accelerator.
2. The electronic device as defined in claim 1 , wherein the at least one hardware accelerator includes a programmable datapath pipeline to filter a first array of values.
3. The electronic device as defined in claim 2 , wherein the at least one hardware accelerator further includes:
a buffer to store a scan-line of an image filtered by the programmable datapath pipeline; and
a pipeline stall controller to stall an operation of the programmable datapath pipeline when the buffer is full.
4. The electronic device as defined in claim 1 , wherein the memory fabric is to:
facilitate first operations by the at least one hardware accelerator on a first array of values; and
facilitate second operations by the at least one vector processor on a second array of values.
5. The electronic device as defined in claim 1 , wherein the memory fabric is to prevent stalling by:
providing a first array of values to the at least one hardware accelerator; and
providing, in parallel with the first array of values, a second array of values to the at least one vector processor.
6. The electronic device as defined in claim 1 , wherein the at least one peripheral device is to provide communication between external devices and at least one of the memory fabric, the at least one vector processor or the at least one hardware accelerator.
7. A system comprising:
a memory fabric including memory slices, the memory fabric structured to allow parallel access to (a) first ones of the memory slices corresponding to at least one vector processor and (b) second ones of the memory slices corresponding to at least one hardware accelerator;
first means for bus communications communicatively connected to the memory fabric, the first means for bus communications to facilitate data transfer between the at least one vector processor and first ones of the memory slices;
second means for bus communications communicatively connected to the memory fabric, the second means for bus communications to facilitate data transfer between the at least one hardware accelerator and second ones of the memory slices; and
third means for bus communications to facilitate data transfer between: (a) peripheral device means and the at least one vector processor, and (b) the at least one vector processor and the at least one hardware accelerator.
8. The system as defined in claim 7 , wherein the at least one hardware accelerator further includes means for programmable pipelining to filter a first array of values.
9. The system as defined in claim 8 , wherein the at least one hardware accelerator further includes:
means for buffering to store a scan-line of an image filtered by the programmable pipelining means; and
means for pipeline control to stall an operation of the programmable pipelining means when the buffering means is full.
10. The system as defined in claim 7 , wherein the memory fabric is to:
facilitate first operations by the at least one hardware accelerator on a first array of values; and
facilitate second operations by the at least one vector processor on a second array of values.
11. The system as defined in claim 7 , wherein the memory fabric is to prevent stalling by:
providing a first array of values to the at least one hardware accelerator; and
provide, in parallel with the first array of values, a second array of values to the at least one vector processor.
12. The system as defined in claim 7 , wherein the peripheral device means is to provide communication between external devices and the at least one of the memory fabric, the at least one vector processor, or the at least one hardware accelerator.
13. A method, comprising:
facilitating first data transfer between at least one vector processor and one or more memory slices of a memory fabric, the memory fabric structured to allow parallel access to (a) first ones of the one or more memory slices corresponding to at least one vector processor and (b) second ones of the one or more memory slices corresponding to at least one hardware accelerator, the first data transfer occurring via a first data bus communicatively connected to the memory fabric, the first data bus to facilitate the first data transfer between the at least one vector processor and first ones of the one or more memory slices;
facilitating second data transfer between the at least one hardware accelerator and second ones of the one or more memory slices of the memory fabric, the second data transfer occurring via a second data bus communicatively connected to the memory fabric; and
facilitating third data transfer between: (a) at least one peripheral device and the at least one vector processor, and (b) the at least one vector processor and the at least one hardware accelerator.
14. The method as defined in claim 13 , further including filtering a first array of values corresponding to a respective one of the at least one hardware accelerator.