Architecture agnostic replay verfication

1. A method, comprising:

generating a live execution trace log corresponding to a live execution of a computer program, the live execution being performed by using both hardware emulation and hardware acceleration;

generating a first trace entry corresponding to a replay execution of the computer program, the replay execution being performed by using hardware emulation without hardware acceleration, the replay execution being performed based on a set of events that are recorded during the live execution of the computer program;

detecting whether the first trace entry is valid based on the live execution trace log, wherein detecting whether the first trace entry is valid includes detecting whether the live execution trace log includes a second trace entry that matches the first trace entry; and

in response to detecting that the first trace entry is not valid, transitioning into a safe state, wherein transitioning into the safe state includes one or more of: (i) generating an indication that the first trace entry is invalid, (ii) outputting the indication on an output device, and (iii) terminating the replay execution of the computer program.

2. The method of claim 1 , further comprising, in response to detecting that the first trace entry is valid, adding the first trace entry to a replay execution trace log.

3. The method of claim 1 , further comprising, in response to detecting that the first trace entry is valid, discarding the first trace entry.

4. The method of claim 1 , wherein generating the live execution trace log includes:

during periods in which hardware acceleration is used to execute the computer program, retrieving hardware trace entries from a hardware trace log and adding the hardware trace entries to the live execution trace log;

during periods in which hardware emulation is used to execute the computer program, generating new trace entries in response to respective requests from a hardware emulator, and adding the new trace entries to the live execution trace log.

5. The method of claim 1 , wherein generating the live execution trace log includes:

detecting a first state transition of the computer program from a hardware-emulated state to a hardware-accelerated state;

in response to the first state transition, periodically retrieving hardware trace entries from a hardware trace log and adding the hardware trace entries to the live execution trace log, the hardware trace entries being periodically retrieved from the hardware trace log and added to the live execution trace log until the computer program transitions back into the hardware-emulated state.

6. The method of claim 1 , wherein the second trace entry matches the first trace entry when: (i) the first trace entry and the second trace entry are associated with a same instruction of the computer program, and (ii) the instruction is executed at the same or proximate point in an execution flow of the computer program during each of the live execution of the computer program and the replay execution of the computer program.

7. A system, comprising:

a memory; and

at least one processor, configured to perform operations of:

generating a live execution trace log corresponding to a live execution of a computer program, the live execution being performed by using both hardware emulation and hardware acceleration;

generating a first trace entry corresponding to a replay execution of the computer program, the replay execution being performed by using hardware emulation without hardware acceleration, the replay execution being performed based on a set of events that are recorded during the live execution of the computer program;

detecting whether the first trace entry is valid based on the live execution trace log, wherein detecting whether the first trace entry is valid includes detecting whether the live execution trace log includes a second trace entry that matches the first trace entry; and

in response to detecting that the first trace entry is not valid, transitioning into a safe state, wherein transitioning into the safe state includes one or more of: (i) generating an indication that the first trace entry is invalid, (ii) outputting the indication on an output device, and (iii) terminating the replay execution of the computer program.

8. The system of claim 7 , wherein the at least one processor is further configured to perform the operation of adding the first trace entry to a replay execution trace log in response to detecting that the first trace entry is valid.

9. The system of claim 7 , wherein the at least one processor is further configured to perform the operation of discarding the first trace entry in response to detecting that the first trace entry is valid.

10. The system of claim 7 , wherein generating the live execution trace log includes:

during periods in which hardware acceleration is used to execute the computer program, retrieving hardware trace entries from a hardware trace log and adding the hardware trace entries to the live execution trace log;

during periods in which hardware emulation is used to execute the computer program, generating new trace entries in response to respective requests from a hardware emulator, and adding the new trace entries to the live execution trace log.

11. The system of claim 7 , wherein generating the live execution trace log includes:

detecting a first state transition of the computer program from a hardware-emulated state to a hardware-accelerated state;

in response to the first state transition, periodically retrieving hardware trace entries from a hardware trace log and adding the hardware trace entries to the live execution trace log, the hardware trace entries being periodically retrieved from the hardware trace log and added to the live execution trace log until the computer program transitions back into the hardware-emulated state.

12. The system of claim 7 , wherein the second trace entry matches the first trace entry when: (i) the first trace entry and the second trace entry are associated with a same instruction of the computer program, and (ii) the instruction is executed at the same or proximate point in an execution flow of the computer program during each of the live execution of the computer program and the replay execution of the computer program.

13. A non-transitory computer-readable medium storing processor executable instructions, which when executed by at least one processor cause the at least one processor to perform the operations of:

generating a live execution trace log corresponding to a live execution of a computer program, the live execution being performed by using both hardware emulation and hardware acceleration;

generating a first trace entry corresponding to a replay execution of the computer program, the replay execution being performed by using hardware emulation without hardware acceleration, the replay execution being performed based on a set of events that are recorded during the live execution of the computer program;

detecting whether the first trace entry is valid based on the live execution trace log, wherein detecting whether the first trace entry is valid includes detecting whether the live execution trace log includes a second trace entry that matches the first trace entry; and

in response to detecting that the first trace entry is not valid, transitioning into a safe state, wherein transitioning into the safe state includes one or more of: (i) generating an indication that the first trace entry is invalid, (ii) outputting the indication on an output device, and (iii) terminating the replay execution of the computer program.

14. The non-transitory computer-readable medium of claim 13 , wherein the processor-executable instructions further cause the at least one processor to perform the operation of adding the first trace entry to a replay execution trace log in response to detecting that the first trace entry is valid.

15. The non-transitory computer-readable medium of claim 13 , wherein the processor-executable instructions further cause the at least one processor to perform the operation of discarding the first trace entry in response to detecting that the first trace entry is valid.

16. The non-transitory computer-readable medium of claim 13 , wherein generating the live execution trace log includes:

during periods in which hardware acceleration is used to execute the computer program, retrieving hardware trace entries from a hardware trace log and adding the hardware trace entries to the live execution trace log;

during periods in which hardware emulation is used to execute the computer program, generating new trace entries in response to respective requests from a hardware emulator, and adding the new trace entries to the live execution trace log.

17. The non-transitory computer-readable medium of claim 13 , wherein generating the live execution trace log includes:

detecting a first state transition of the computer program from a hardware-emulated state to a hardware-accelerated state;

in response to the first state transition, periodically retrieving hardware trace entries from a hardware trace log and adding the hardware trace entries to the live execution trace log, the hardware trace entries being periodically retrieved from the hardware trace log and added to the live execution trace log until the computer program transitions back into the hardware-emulated state.

18. The non-transitory computer-readable medium of claim 13 , wherein

the second trace entry matches the first trace entry when: (i) the first trace entry and the second trace entry are associated with a same instruction of the computer program, and (ii) the instruction is executed at the same or proximate point in an execution flow of the computer program during each of the live execution of the computer program and the replay execution of the computer program.