IP Library Granted Patent US 10,991,668
Granted Patent B1
US 10,991,668 · App. 16/720,876 · Granted Apr 27, 2021

Connection pad configuration of semiconductor device

Inventors: Tsuyoshi Koga (Tokyo, JP); Shinya Suzuki (Tokyo, JP); Naoki Hasegawa (Tokyo, JP); Naoyuki Narita (Tokyo, JP); Kiyotaka Miwa (Tokyo, JP); Kazuhiko Sato (Tokyo, JP); Yuichi Nakagomi (Tokyo, JP)
Assignee: Synaptics Incorporated
H01L24/13H01L23/3128H01L24/05
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Quick Facts
Patent No.
US 10,991,668
App. No.
16/720,876
Granted
Apr 27, 2021
Kind
B1
Abstract

A semiconductor device comprises a semiconductor substrate, a connection pad, and a bump. The connection pad is connected to the bump and disposed between the semiconductor substrate and the bump. The connection pad has one or more slits.

Claims (47)

1. A semiconductor device comprising:

a semiconductor substrate;

a bump; and

a connection pad connected to the bump and disposed between the semiconductor substrate and the bump, the connection pad having one or more slits,

wherein the one or more slits comprise a plurality of first slits arrayed in a longitudinal direction of the connection pad and wherein each of the plurality of first slits has first geometric centers positioned on a first straight line extending in the longitudinal direction.

2. The semiconductor device according to claim 1 , wherein the connection pad is elongated in a longitudinal direction, and

wherein the one or more slits are extended in a first direction orthogonal to the longitudinal direction of the connection pad.

3. The semiconductor device according to claim 1 , wherein the one or more slits are extended in a longitudinal direction of the connection pad.

4. The semiconductor device according to claim 1 , wherein the plurality of first slits are extended in a first direction orthogonal to the longitudinal direction of the connection pad.

5. The semiconductor device according to claim 1 , wherein lengths of the plurality of first slits are longer than one-third of a width of the connection pad in the first direction.

6. The semiconductor device according to claim 1 , wherein the first straight line comprises a center line of the connection pad.

7. The semiconductor device according to claim 1 , wherein the one or more slits further comprises a plurality of second slits arrayed in the longitudinal direction of the connection pad, and

wherein each of the plurality of second slits has second geometric centers aligned on a second straight line extending in the longitudinal direction, the second straight line being different from the first straight line.

8. The semiconductor device according to claim 7 , wherein the plurality of first slits and the plurality of second slits are extended in a first direction orthogonal to the longitudinal direction of the connection pad.

9. The semiconductor device according to claim 8 , wherein lengths of the plurality of first slits and lengths the plurality of second slits are longer than one sixth of a width of the connection pad in the first direction.

10. The semiconductor device according to claim 7 , wherein the plurality of first slits and the plurality of second slits are extended in the longitudinal direction of the connection pad.

11. The semiconductor device according to claim 1 , wherein the one or more slits comprises a plurality of slits spaced at equal intervals.

12. The semiconductor device according to claim 11 , further comprising a passivation layer comprising an opening through which the bump is connected to the connection pad,

wherein the plurality of slits are positioned in a second direction with respect to the opening, the second direction being parallel to a longitudinal direction of the connection pad.

13. The semiconductor device according to claim 1 , wherein the one or more slits have an open end and a closed end.

14. A semiconductor device comprising:

a semiconductor substrate;

a bump; and

a connection pad connected to the bump and disposed between the semiconductor substrate and the bump, the connection pad having one or more slits;

a passivation layer comprising an opening through which the bump is connected to the connection pad,

wherein the one or more slits comprises:

a first slit positioned in a second direction parallel to a longitudinal direction of the connection pad with respect to the opening; and

a second slit positioned in a third direction opposite to the second direction with respect to the opening.

15. A semiconductor device comprising:

a semiconductor substrate;

a bump; and

a connection pad connected to the bump and disposed between the semiconductor substrate and the bump, the connection pad having one or more slits,

wherein the one or more slits comprises a first slit and a second slit extended in a first direction orthogonal to a longitudinal direction of the connection pad,

wherein the first slit has a first open end in the first direction and a first closed end in a second direction opposite to the first direction, and

wherein the second slit has a second open end in the second direction and a second closed end in the first direction.

16. A method comprising:

preparing a semiconductor substrate;

forming a connection pad comprising one or more slits over the semiconductor substrate, wherein the one or more slits comprise a plurality of first slits arrayed in a longitudinal direction of the connection pad and wherein each of the plurality of first slits has first geometric centers positioned on a first straight line extending in the longitudinal direction; and

forming a bump over the connection pad, wherein the bump is connected to the connection pad.

17. The method according to claim 16 , wherein the connection pad is elongated in a longitudinal direction, and

wherein the one or more slits are extended in a first direction orthogonal to the longitudinal direction of the connection pad.

18. A semiconductor device comprising:

a semiconductor substrate;

a bump; and

a connection pad connected to the bump and disposed between the semiconductor substrate and the bump, the connection pad having one or more slits,

wherein the connection pad comprises a narrow portion and a wide portion, and wherein one or more of the one or more slits is positioned in the wide portion.

19. The semiconductor device according to claim 18 , wherein the narrow portion is extended from the wide portion along a center line of the connection pad.

Assignments (2)
SECURITY INTEREST Recorded Feb 14, 2020
From: SYNAPTICS INCORPORATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 051936/0103 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2019
From: KOGA, TSUYOSHI; SUZUKI, SHINYA; HASEGAWA, NAOKI; NARITA, NAOYUKI; MIWA, KIYOTAKA; SATO, KAZUHIKO; NAKAGOMI, YUICHI
To: SYNAPTICS INCORPORATED
Reel/Frame 051334/0404 →