Semiconductor device including silicon carbide body and method of manufacturing

1. A semiconductor device comprising a silicon carbide body that comprises:

a first section and a second section, wherein the first section is adjacent to the second section;

a drift region formed in the first section and the second section; and

a lattice defect region in a portion of the drift region in the second section, wherein a first density of lattice defects comprising interstitials and vacancies in the lattice defect region is at least double a second density of lattice defects comprising interstitials and vacancies in a portion of the drift region outside the lattice defect region.

2. The semiconductor device according to claim 1 , wherein

the lattice defect region is absent in at least a portion of the first section.

3. The semiconductor device according to claim 1 , comprising:

an emitter region in the second section, wherein the emitter region is between a first surface of the silicon carbide body and the drift region and wherein the emitter region and the drift region form a main pn junction; and

a unipolar current region in the first section, wherein the unipolar current region is between the first surface and the drift region and wherein the unipolar current region comprises at least one of a body region of a transistor cell or a cathode region of a Schottky contact.

4. The semiconductor device according to claim 3 , wherein

the lattice defect region comprises an upper defect region in a part of the drift region within a threshold distance of the main pn junction.

5. The semiconductor device according to claim 4 , wherein

the upper defect region overlaps the main pn junction.

6. The semiconductor device according to claim 1 , wherein

the silicon carbide body comprises a base portion between a second surface of the silicon carbide body and the drift region, wherein the base portion and the drift region form a rear side junction and wherein the lattice defect region comprises a lower defect region in a part of the drift region within a threshold distance of the rear side junction.

7. The semiconductor device according to claim 6 , wherein

the lower defect region overlaps the rear side junction.

8. The semiconductor device according to claim 1 , wherein

the lattice defect region comprises a plurality of parallel stripe portions.

9. The semiconductor device according to claim 8 , comprising:

a plurality of stripe-shaped unipolar current regions,

wherein the plurality of parallel stripe portions run parallel to the plurality of stripe-shaped unipolar current regions.

10. The semiconductor device according to claim 8 , comprising

a plurality of stripe-shaped unipolar current regions,

wherein the plurality of parallel stripe portions run transverse to the plurality of stripe-shaped unipolar current regions.

11. The semiconductor device according to claim 1 , wherein

a plurality of unipolar current regions are arranged in rows and columns and wherein the lattice defect region forms a grid with the plurality of unipolar current regions formed in meshes of the grid.

12. The semiconductor device according to claim 1 , wherein

the first section comprises a body region of a transistor cell.

13. The semiconductor device according to claim 1 , wherein

the first section comprises a Schottky contact.

14. A method of manufacturing a semiconductor device, the method comprising:

providing a silicon carbide substrate comprising a first section and a second section, wherein the first section is adjacent to the second section, wherein the silicon carbide substrate comprises a drift layer in the first section and the second section; and

forming a lattice defect region in a portion of the drift layer in the second section, wherein a first density of lattice defects comprising interstitials and vacancies in the lattice defect region is at least double a second density of lattice defects comprising interstitials and vacancies in a portion of the drift layer outside the lattice defect region.

15. The method according to claim 14 , wherein

the lattice defect region is not formed in at least a portion of the first section.

16. The method according to claim 14 , wherein

forming the lattice defect region comprises implanting at least one of hydrogen (H), helium (He) or argon (Ar) into the second section through a patterned implant mask.

17. The method according to claim 14 , comprising:

performing a heat treatment for activating implanted dopants;

implanting at least one of hydrogen (H), helium (He) or argon (Ar) after performing the heat treatment; and

forming a gate trench extending from a main surface of the silicon carbide substrate into the silicon carbide substrate after implanting the at least one of H, He or Ar.

18. The method according to claim 14 , comprising:

forming a gate trench extending from a main surface of the silicon carbide substrate into the silicon carbide substrate;

implanting at least one of hydrogen (H), helium (He) or argon (Ar) after forming the gate trench; and

forming a gate dielectric layer along a sidewall of the gate trench after implanting the at least one of H, He or Ar.

19. The method according to claim 14 , comprising:

forming a first metal layer on a main surface of the silicon carbide substrate;

implanting at least one of hydrogen (H), helium (He) or argon (Ar) after forming the first metal layer; and

forming a second metal layer on the first metal layer after implanting the at least one of H, He or Ar.

20. The method according to claim 14 , comprising:

forming a second metal layer on a main surface of the silicon carbide substrate; and

implanting at least one of hydrogen (H), helium (He) or argon (Ar) after forming the second metal layer.